Journal ArticleDOI
Power7: IBM's Next-Generation Server Processor
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TLDR
Power Systems™ continue strong 7th Generation Power chip: Balanced Multi-Core design EDRAM technology SMT4 greater then 4X performance in same power envelope as previous generation.Abstract:
The Power7 is IBM's first eight-core processor, with each core capable of four-way simultaneous-multithreading operation. Its key architectural features include an advanced memory hierarchy with three levels of on-chip cache; embedded-DRAM devices used in the highest level of the cache; and a new memory interface. This balanced multicore design scales from 1 to 32 sockets in commercial and scientific environments.read more
Citations
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Journal ArticleDOI
Single-chip microprocessor that communicates directly using light
Chen Sun,Chen Sun,Mark T. Wade,Yunsup Lee,Jason S. Orcutt,Jason S. Orcutt,Luca Alloatti,Michael Georgas,Andrew Waterman,Jeffrey M. Shainline,Jeffrey M. Shainline,Rimas Avizienis,Sen Lin,Benjamin Moss,Rajesh Kumar,Fabio Pavanello,Amir H. Atabaki,Henry Cook,Albert Ou,Jonathan Leu,Yu-Hsin Chen,Krste Asanovic,Rajeev J. Ram,Milos A. Popovic,Vladimir Stojanovic +24 more
TL;DR: This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Journal ArticleDOI
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory
TL;DR: The studies based on the proposed scaling methodology show that in-plane STT-MRAM will outperform SRAM from 15 nm node, while its perpendicular counterpart requires further innovations in MTJ material in order to overcome the poor write performance scaling from 22 nm node onwards.
Journal ArticleDOI
Understanding POWER multiprocessors
TL;DR: An abstract-machine semantics that abstracts from most of the implementation detail but explains the behaviour of a range of subtle examples of IBM POWER multiprocessors is given, which should bring new clarity to concurrent systems programming for these architectures.
Proceedings ArticleDOI
PHANTOM: practical oblivious computation in a secure processor
Martin Maas,Eric Love,Emil Stefanov,Mohit Tiwari,Elaine Shi,Krste Asanovic,John Kubiatowicz,Dawn Song +7 more
TL;DR: PHANTOM is the first demonstration of a practical, oblivious processor that can provide strong confidentiality guarantees when offloading computation to the cloud and is efficient in both area and performance.
Proceedings ArticleDOI
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
TL;DR: In this article, the relative merits between different approaches in the face of technology constraints are analyzed for U-cores and the predictive power of their model depends upon U-core-specific parameters derived by measuring performance and power of tuned applications on today's state-of-the-art multicores, GPUs, FPGAs, and ASICs.
References
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Journal ArticleDOI
POWER4 system microarchitecture
TL;DR: The processor microarchitecture as well as the interconnection architecture employed to form systems up to a 32-way symmetric multiprocessor are described.
Journal ArticleDOI
IBM Power5 chip: a dual-core multithreaded processor
TL;DR: The approach to improve chip-level performance of the Power5 was described, which specified increased performance and other functional enhancements of server virtualization, reliability, availability, and serviceability at both chip and system levels.
Journal ArticleDOI
POWER5 System microarchitecture
TL;DR: This paper describes the implementation of the IBM POWER5TM chip, a two-way simultaneous multithreaded dual-core chip, and systems based on it, and how it allows system scalability to 64 physical processors.
Journal ArticleDOI
IBM POWER6 microarchitecture
Hung Qui Le,William J. Starke,J. S. Fields,Francis Patrick O'Connell,D. Q. Nguyen,B. J. Ronchetti,Wolfram Sauer,Eric M. Schwarz,Michael Thomas Vaden +8 more
TL;DR: Key extensions to the coherence protocol enable POWER6 microprocessor-based systems to achieve better SMP scalability while enabling reductions in system packaging complexity and cost.
Proceedings Article
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
John E. Barth,William Robert Reohr,Paul C. Parries,Gregory J. Fredeman,John W. Golz,Stanley E. Schuster,Richard E. Matick,Hillery C. Hunter,Charles C. Tanner,Joseph Harig,Hoki Kim,Babar A. Khan,John Griesemer,Robert P. Havreluk,Kenji Yanagisawa,Toshiaki Kirihata,Subramanian S. Iyer +16 more
TL;DR: In this article, the authors describe a 500MHz random cycle Silicon on Insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over traditional array design methods.