Practical application of full-feature alternating phase-shifting technology for a phase-aware standard-cell design flow
22 Jun 2001-pp 93-96
TL;DR: This paper presents a methodology targeted for standard-cell or structured-custom design styles that start from standard-cells created in a manner in which all issues regarding generation of AltPSM are effectively considered, and are then used in a typical cell-based (synthesis-automatic place and route) flow to produce design layouts that are ready for cost-effective silicon manufacturing.
Abstract: As the semiconductor industry enters the subwavelength era where silicon features are much smaller that the wavelength of the light used to create them, a number of “subwavelength” technologies such as Optical Proximity Correction (OPC) and Phase-Shifting Masks (PSM) have been introduced to produce integrated circuits (ICs) with acceptable yields. An effective approach to subwavelength IC production includes a combination of these techniques, including OPC and PSM. Nevertheless, as we approach silicon features of 0.10&mgr and below, Alternating PSM (AltPSM) becomes a critical part of the technology portfolio needed to achieve IC requirements. An effective EDA methodology that generates AltPSM ICs must guarantee correct generation of AltPSM layouts, maintain or improve today's design productivity, and leverage existing tools and flows. The implementation of such a methodology becomes more complex as phase shifting is applied to all critical features, including those outside of transistor gates. In this paper, we present a methodology targeted for standard-cell or structured-custom design styles. We also present examples of designs that start from standard-cells created in a manner in which all issues regarding generation of AltPSM are effectively considered, and are used in a typical cell-based (synthesis-Automatic Place & Route) flow to produce design layouts that are ready for cost-effective silicon manufacturing.
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TL;DR: A novel selective CS architecture for energy-efficient wireless implantable neural decoding based on compression analysis and deep learning is proposed, which can gain more than 60% energy savings than the conventional CS architecture, yet improve the accuracy of state-of-the-art CS architectures.
Abstract: The spike classification is a critical step in the implantable neural decoding. The energy efficiency issue in the sensor node is a big challenge for the entire system. Compressive sensing (CS) theory provides a potential way to tackle this problem by reducing the data volume on the communication channel. However, the constant transmission of the compressed data is still energy-hungry. On the other hand, the feasibility of direct analysis in compression domain is mathematically demonstrated. This advance empowers the in-sensor light-weight signal analysis on the compressed data. In this paper, we propose a novel selective CS architecture for energy-efficient wireless implantable neural decoding based on compression analysis and deep learning. Specifically, we develop a two-stage classification procedure, including a light-weight coarse-grained screening module in the sensor and an accurate fine-grained analysis module in the server. To achieve better energy efficiency, the screening module is designed by the Softmax regression, which can complete the low-effort classification task at the sensor end and screen the high-effort task to transmit their compressed measurements to the remote server. The fine-grained analysis located in server end is constructed by the customized deep residual neural network. It can not only promote the spike classification accuracy, but also benefit the model quality of in-sensor Softmax model. The extensive experimental results indicate that our proposed selective CS architecture can gain more than 60% energy savings than the conventional CS architecture, yet even improve the accuracy of state-of-the-art CS architectures.
8 citations
Cites methods from "Practical application of full-featu..."
...We use TSMC 90nm standard cell libraries [48] and implement the design in Verilog with Verilog Compile Simulator (VCS)....
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Patent•
08 Mar 2002
TL;DR: In this paper, the phase shifter placement is subject to coloring constraints and the phase shifting priorities of the zones are assigned to zones associated with different priorities of phase shifters during the phase shift process.
Abstract: One embodiment of the invention provides a method that facilitates selectively varying how much of a layout of an integrated circuit is defined by phase shifters during an optical lithography process used in manufacturing the integrated circuit. During operation, the method receives a specification of the layout of the integrated circuit. The method then assigns features within the layout to zones associated with different phase shifting priorities. Next, the method generates a phase shifter placement by placing phase shifters comprised of phase shifting geometries onto a phase shifting mask to define the features within the layout, wherein the phase shifter placement is subject to coloring constraints. Note that in general there is no restriction on the order of zone placement. During this placement process, if coloring constraints cannot be satisfied, the method resolves conflicts and/or removes features from being phase-shifted based upon phase shifting priorities of the zones.
6 citations
Patent•
06 Jun 2001TL;DR: In this article, a system for generating trim to be used in conjunction with phase shifters during an optical lithography process for manufacturing an integrated circuit is described, where the system operates by identifying a feature within the integrated circuit to be created by using a phase shifter to produce a region of destructive light interference.
Abstract: One embodiment of the invention provides a system for generating trim to be used in conjunction with phase shifters during an optical lithography process for manufacturing an integrated circuit The system operates by identifying a feature within the integrated circuit to be created by using a phase shifter to produce a region of destructive light interference on a photoresist layer Next, the system generates the phase shifter for a first mask, while ensuring that design rules are satisfied in defining dimensions for the phase shifter After the phase shifter is generated, the system generates trim within a second mask, that is used in conjunction with the first mask, by deriving the trim from the previously-defined dimensions of the phase shifter while ensuring that the design rules are satisfied Note that the design rules can be satisfied by cutting and/or patching portions of the phase shifter and associated trim
4 citations
Patent•
06 Dec 2002TL;DR: In this paper, the authors present a system and a method for reducing line end shortening during an optical lithography process for manufacturing an integrated circuit, which operates by receiving a specification of the integrated circuit and identifying a gate within the specification, wherein the gate includes an endcap that is susceptible to line-end shortening.
Abstract: One embodiment of the invention provides a system and a method for reducing line end shortening during an optical lithography process for manufacturing an integrated circuit. The system operates by receiving a specification of the integrated circuit, wherein the specification defines transistors that include gates. Next, the system identifies a gate within the specification, wherein the gate includes an endcap that is susceptible to line end shortening during the optical lithography process. The system then extends a phase shifter used to form the gate, so that the phase shifter defines at least a portion of the endcap and thereby reduces line end shortening of the endcap due to optical effects.
3 citations
24 Mar 2003
TL;DR: A new design for manufacturability (DFM) approach is presented, creating an abstract set of rules that can be used to advantage in various IC CAD tool domains, especially for 100 nm and below design rules.
Abstract: Since the semiconductor industry hit the 0.18-micron generation, device feature sizes have become increasingly smaller than the wavelength of light used by available optical-lithography equipment. In this subwavelength arena, manufacturing requirements must be handled up front in the IC design stage-while changes can still be made-to enhance quality and yield. This paper defines the components needed to get clean alternating phase-shifting masks (altPSM) that ensure the manufacturability of subwavelength circuit designs. The authors present a new design for manufacturability (DFM) approach, creating an abstract set of rules that can be used to advantage in various IC CAD tool domains, especially for 100 nm and below design rules. A new methodology and algorithm are presented that can quickly and easily integrate altPSM into existing and future tools earlier in the IC design flow. Finally, experimental results show how the methodology and algorithm is used to debug process-aware designs and make them altPSM-compliant.
3 citations
Cites background from "Practical application of full-featu..."
...Previous research has proposed doing this in the library flow [6]....
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References
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Journal Article•
TL;DR: The phase-shifting mask as mentioned in this paper consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite.
Abstract: The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.
705 citations
"Practical application of full-featu..." refers methods in this paper
...An 8051 microcontroller design is then synthesized to this library....
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IBM1
TL;DR: The phase-shifting mask as mentioned in this paper consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite.
Abstract: The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10X tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.
667 citations
01 Jun 1999
TL;DR: This tutorial paper surveys the potential implications of subwavelength optical lithography for new tools and flows in the interface between layout design and manufacturability and addresses the necessary changes in the design-to-manufacturing flow.
Abstract: This tutorial paper surveys the potential implications of subwavelength optical lithography for new tools and flows in the interface between layout design and manufacturability. We review control of optical process effects by optical proximity correction (OPC) and phase-shifting masks (PSM), then focus on the implications of OPC and PSM for layout synthesis and verification methodologies. Our discussion addresses the necessary changes in the design-to-manufacturing flow, including infrastructure development in the mask and process communities, evolution of design methodology, and opportunities for research and development in the physical layout and verification areas of EDA.
70 citations
29 Jun 1998
TL;DR: In this paper, the results of experimental patterning 140 nm poly gates with double-exposure alternating phase-shifting masks (PSM) using a Nikon EX-1 (KrF,0.42NA) stepper are presented.
Abstract: In this paper we present the results of experimental patterning 140 nm poly gates withdouble-exposure alternating phase-shifting masks (PSM) using a Nikon EX- 1 (KrF,0.42NA) stepper. We show that: systematic intrafield line width variations can becontrolled within 10 nm (3), interfield variations across the wafer to within 6 nm (3),and total variation across the wafer held to within 15 nm (3), with a target k1 factor of k1=0.237 (140 nm target gate lengths). We also present the results of studies addressingseveral issues related to the production application of alternating PSM' s, including mask manufacturing tolerances and full chip PSM design capabilities. We show that, incomparison to conventional binary masks, alternating PSM's reduce the criticality of mask line width control and reduce the sensitivity to mask defects. Furthermore tolerance to PSM phase errors can be significantly improved by placing a chrome regulator between phase-shifters. Automatic, high-speed full chip design of alternating strong PSMis now possible.Keywords: Optical lithography, Phase-shifting masks, line width variations, CD control
62 citations
12 Feb 1997
TL;DR: In this article, the problem of intra-field line width variations can be effectively solved through a novel application of alternating phase-shifting mask (PSM) technology, which is applied to produce 140 nm transistor gates using DUV (248 nm wavelength, KrF) lithography.
Abstract: In this paper we show that the problem of intrafield line width variations can be effectively solved through a novel application of alternating phase-shifting mask (PSM) technology. To illustrate its advantages, we applied this approach to produce 140 nm transistor gates using DUV (248 nm wavelength, KrF) lithography. We show that: systematic intrafield line width variations can be controlled to within 10 nm (3 (sigma) ), and variations across the wafer held to within 15 nm (3 (sigma) ), with a target k1 factor of K1 equals 0.237 (140 nm target gate lengths).
45 citations