Practical Design Considerations for MV LCL Filter Under High dv/dt Conditions Considering the Effects of Parasitic Elements
01 Jun 2018-
TL;DR: In this paper, the effect of high dv/dt on the filter and the effectiveness of the proposed solution are validated using simulation and experimental data is also provided to validate the proposed concept.
Abstract: For high power medium voltage (MV) grid connected applications LCL filter proves to be an attractive solution to filter out the current harmonics when compared to $L$ or LC filters. The inductance requirement reduces drastically to meet the same Total Harmonic Distortion (THD) standards for grid connections for LC L filters compared to $L$ filter which makes the system dynamics much faster. The increasing use of Silicon Carbide (SiC) based power devices for MV applications has made the effects of the parasitic elements in the filter more prominent, due to the high dv / dt experienced by the passive filter elements during device switching transients. This paper addresses the issues associated with the high dv / dt experienced by the LC L filters for SiC-based MV applications. In order to study these effects, the parasitic elements of the inductor are modeled and analyzed. A suitable solution is proposed to improve the overall system performance. The effect of high dv / dt on the filter and the effectiveness of the proposed solution are validated using simulation. Experimental data is also provided to validate the proposed concept.
Citations
More filters
TL;DR: In this paper, a general physics-based model for identifying the parasitic capacitance in medium-voltage (MV) filter inductors is proposed, which can provide analytical calculations without using empirical equations and is not restricted by the geometrical structures of inductors.
Abstract: This article proposes a general physics-based model for identifying the parasitic capacitance in medium-voltage (MV) filter inductors, which can provide analytical calculations without using empirical equations and is not restricted by the geometrical structures of inductors The elementary capacitances of the MV inductor are identified, then the equivalent capacitances between the two terminals of the inductor are derived under different voltage potential on the core Further, a three-terminal equivalent circuit, instead of the conventional two-terminal equivalent circuit, is proposed by using the derived capacitances Thus, the parasitic equivalent capacitance between the terminals and the core are explicitly quantified Experimental measurements for parasitic capacitances show a good agreement with the theoretical calculations
37 citations
TL;DR: In this article, a physics-based analytical modeling method for the parasitic capacitances contributed by the fringe electrical field is proposed, which avoids using any empirical equations and shows a close agreement with the measured capacitance by using an impedance analyzer.
Abstract: This article characterizes three parasitic capacitances in copper-foiled medium-voltage inductors. It is found that the conventional modeling method overlooks the effect of the fringe field, which leads to inaccurate modeling of parasitic capacitances in copper-foiled inductors. To address this problem, the parasitic capacitances contributed by the fringe electrical field is identified first, and a physics-based analytical modeling method for the parasitic capacitances contributed by the fringe electrical field is proposed, which avoids using any empirical equations. The total parasitic capacitances are then derived for three different cases with three different core potentials, from which a three-terminal equivalent circuit is derived, and thus, the parasitic capacitances in copper-foiled inductors are explicitly identified. The calculated results show a close agreement with the measured capacitance by using an impedance analyzer. Two recommendations for reducing the parasitic capacitances in copper-foiled inductors are given in this article.
20 citations
01 Sep 2018
TL;DR: In this article, the authors provide an overview of a MUSE-SST topology and a brief idea on control and monitoring is provided to aid researchers in designing converters for medium voltage (MV) applications.
Abstract: With the increasing maturity of Silicon Carbide (SiC) semiconductor devices at medium voltage (MV) level, high switching frequencies and low conduction losses in MV applications is possible. Higher switching frequency operation enables the reduction in size and weight of transformers. In an application such as MV-MV or MV-LV grid-interconnection, a solid state transformer offers a multitude of advantages compared to conventional transformers. A reduction in size and weight, in addition to having active and reactive power flow control have made SSTs a lucrative replacement to conventional low frequency (LF) transformers. Lower conduction losses exhibited by SiC devices (as compared to their silicon counterparts) have made it possible to achieve similar efficiencies as compared to conventional LF transformers. This paper aims at providing an overview of a MV MUSE-SST topology. A brief idea on control and monitoring is also provided. Practical design considerations that are required to build a MV system is provided to aid researchers in designing converters for MV applications. The protection aspects of the MV MUSE-SST system is also highlighted. Basic experimental results for the gate driver is also shown. Initial testing results with the Gen3 10 kV SiC MOSFETs and the challenges associated with it are also discussed. This research aims at being a building block for implementation and testing of the medium voltage converter systems.
17 citations
Cites background or methods from "Practical Design Considerations for..."
...The experiment has been done on a buck converter to validate the effect of the parasitic capacitor on the inductor [17]....
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...The parasitic capacitances across the filter inductors and the high frequency transformer leads to an additional current [17]....
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TL;DR: In this article, the effect of parasitic capacitance across the components to be of paramount importance since an additional current flows through the components and, consequently, through the switching device is analyzed.
Abstract: In recent years, the use of silicon carbide (SiC) power semiconductor devices in medium-voltage (MV) applications has been made possible due to the development of high blocking voltage (10–15 kV)-based devices. While the use of these devices brings in a lot of advantages, the semiconductor devices are exposed to high peak stress (of up to 15 kV) and a very high $dv/dt$ (of up to 100 kV/ $\mu \text{s}$ ). The high $dv/dt$ across the devices leads to a high $dv/dt$ across other components connected to the system. This makes the effect of the parasitic capacitance across the components to be of paramount importance since an additional current flows through the components and, consequently, through the switching device. This additional current flows during each switching transition and leads to increased switching losses in the device. This article analyzes the effect of these additional losses on the lifetime of the device. The thermal performance of a three-phase inverter power block is provided, and a mission profile (solar irradiance and temperature)-based analysis is carried out to account for the additional junction temperature rise. The rainflow counting method is implemented to identify the mean and amplitude of each thermal cycle. An empirical device lifetime model is used to calculate the number of cycles to failure. Finally, the Palgrem Miner rule is used to quantify the total damage in the device. Comparisons have been carried out on basis of lifetime for both the cases (with and without the influence of parasitic capacitances). This analysis can be helpful in validating the importance of the design of filter inductors in these MV applications.
16 citations
Cites background from "Practical Design Considerations for..."
...which makes the system dynamics much faster [12]–[14]....
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...It should be noted that due to the MV requirement, inherently, the parasitic capacitance of the inductor goes up and series connecting a number of inductors helps in the reduction of the effective parasitic capacitance [12]....
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TL;DR: In this paper, a behavioral model for analyzing the ground current in medium-voltage (MV) inductors is proposed, where the impedance between the terminals and the ground connection of inductors are measured by the impedance analyzer.
Abstract: This letter proposes a behavioral model for analyzing the ground current in medium-voltage (MV) inductors. The impedance between the terminals and the ground connection of inductors is measured by the impedance analyzer, which is capacitive at low frequency. In order to characterize this impedance, a multistage paralleled RLC circuit is proposed. An analytical method is further developed to calculate parameters of the proposed equivalent circuit, which enables to predict the time-domain response of the ground current in MV inductors. A digital twin of the double-pulse-test setup is developed in LTspice, where the simulated ground currents show good agreements with the experimental measurements.
15 citations
Cites background from "Practical Design Considerations for..."
...This poses much challenge to the design of MV filter inductors, whose parasitic capacitive couplings become more significant than other components because of the high inductance resulted from more turns [4]....
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References
More filters
30 Sep 2001
TL;DR: In this article, a step-by-step procedure for designing the LCL filter of a front-end three-phase active rectifier is proposed to reduce the switching frequency ripple at a reasonable cost, while at the same time achieving a high-performance front end rectifier.
Abstract: This paper proposes a step-by-step procedure for designing the LCL filter of a front-end three-phase active rectifier. The primary goal is to reduce the switching frequency ripple at a reasonable cost, while at the same time achieving a high-performance front-end rectifier (as characterized by a rapid dynamic response and good stability margin). An example LCL filter design is reported and a filter has been built and tested using the values obtained from this design. The experimental results demonstrate the performance of the design procedure both for the LCL filter and for the rectifier controller. The system is stable and the grid current harmonic content is low both in the lowand high-frequency ranges. Moreover, the good agreement that was obtained between simulation and experimental results validates the proposed approach. Hence, the design procedure and the simulation model provide a powerful tool to design an LCL-filter-based active rectifier while avoiding trial-and-error procedures that can result in having to build several filter prototypes.
2,147 citations
"Practical Design Considerations for..." refers background in this paper
...However, for applications above several kilowatts, it becomes expensive to realize these filter reactors [5]....
[...]
TL;DR: In this article, two types of pulsewidth-modulated modular multilevel converters (PWM-MMCs) with focus on their circuit configurations and voltage balancing control are investigated.
Abstract: A modular multilevel converter (MMC) is one of the next-generation multilevel converters intended for high- or medium-voltage power conversion without transformers. The MMC is based on cascade connection of multiple bidirectional chopper-cells per leg, thus requiring voltage-balancing control of the multiple floating DC capacitors. However, no paper has made an explicit discussion on voltage-balancing control with theoretical and experimental verifications. This paper deals with two types of pulsewidth-modulated modular multilevel converters (PWM- MMCs) with focus on their circuit configurations and voltage-balancing control. Combination of averaging and balancing controls enables the PWM-MMCs to achieve voltage balancing without any external circuit. The viability of the PWM-MMCs, as well as the effectiveness of the voltage-balancing control, is confirmed by simulation and experiment.
1,506 citations
"Practical Design Considerations for..." refers background in this paper
...This eliminates the need of complicated multi-level topologies which relies on the circuit level solutions to go to higher voltage levels where many number of converter blocks are connected in series [2]....
[...]
TL;DR: In this paper, a robust control strategy for regulating the grid current entering a distribution network from a three-phase VSI system connected via a LCL filter is proposed, which integrates an outer loop grid current regulator with inner capacitor current regulation to stabilize the system.
Abstract: Many grid connected power electronic systems, such as STATCOMs, UPFCs, and distributed generation system interfaces, use a voltage source inverter (VSI) connected to the supply network through a filter. This filter, typically a series inductance, acts to reduce the switching harmonics entering the distribution network. An alternative filter is a LCL network, which can achieve reduced levels of harmonic distortion at lower switching frequencies and with less inductance, and therefore has potential benefits for higher power applications. However, systems incorporating LCL filters require more complex control strategies and are not commonly presented in literature. This paper proposes a robust strategy for regulating the grid current entering a distribution network from a three-phase VSI system connected via a LCL filter. The strategy integrates an outer loop grid current regulator with inner capacitor current regulation to stabilize the system. A synchronous frame PI current regulation strategy is used for the outer grid current control loop. Linear analysis, simulation, and experimental results are used to verify the stability of the control algorithm across a range of operating conditions. Finally, expressions for ""harmonic impedance" of the system are derived to study the effects of supply voltage distortion on the harmonic performance of the system.
869 citations
TL;DR: This paper provides a systematic approach to the design of filter-based active damping methods with tuning procedures, performance, robustness, and limitations discussed with theoretical analysis, selected simulation, and experimental results.
Abstract: Pulsewidth modulation (PWM) voltage source converters are becoming a popular interface to the power grid for many applications. Hence, issues related to the reduction of PWM harmonics injection in the power grid are becoming more relevant. The use of high-order filters like LCL filters is a standard solution to provide the proper attenuation of PWM carrier and sideband voltage harmonics. However, those grid filters introduce potentially unstable dynamics that should be properly damped either passively or actively. The second solution suffers from control and system complexity (a high number of sensors and a high-order controller), even if it is more attractive due to the absence of losses in the damping resistors and due to its flexibility. An interesting and straightforward active damping solution consists in plugging in, in cascade to the main controller, a filter that should damp the unstable dynamics. No more sensors are needed, but there are open issues such as preserving the bandwidth, robustness, and limited complexity. This paper provides a systematic approach to the design of filter-based active damping methods. The tuning procedures, performance, robustness, and limitations of the different solutions are discussed with theoretical analysis, selected simulation, and experimental results.
580 citations
07 Nov 2002
TL;DR: In this article, the authors proposed a robust control strategy for regulating the grid current entering a distribution network from a three-phase VSI system connected via an LCL filter. But, the LCL filters require more complex control strategies and are not commonly presented in literature.
Abstract: Many grid connected power electronic systems, such as STATCOMs, UPFCs and distributed generation system interfaces, use a voltage source inverter (VSI) connected to the supply network through a filter. This filter, typically a series inductance, acts to reduce the switching harmonics entering the distribution network. An alternative filter is a LCL network, which can achieve reduced levels of harmonic distortion at lower switching frequencies and with less inductance, and therefore has potential benefits for higher power applications. However, systems incorporating LCL filters require more complex control strategies and are not commonly presented in literature. This paper proposes a robust strategy for regulating the grid current entering a distribution network from a three-phase VSI system connected via an LCL filter. The strategy integrates an outer loop grid current regulator with inner capacitor current regulation to stabilise the system. A synchronous frame PI current regulation strategy is used for the outer grid current control loop. Linear analysis, simulation and experimental results are used to verify the stability of the control algorithm across a range of operating conditions. Finally, expressions for "harmonic impedance" of the system are derived to study the effects of supply voltage distortion on the harmonic performance of the system.
449 citations