Predictive effective mobility model for FDSOI transistors using technology parameters

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.

An Effective Method to Compensate Total Ionizing Dose-Induced Degradation on Double-SOI Structure

Abstract: The existence of buried oxide (BOX) layer and the strong coupling effect between the front and back channels can worsen the radiation-induced degradation on fully depleted silicon-on-insulator (FDSOI) device. To mitigate the radiation impact, a new structure named double SOI is introduced in this paper. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the BOX layer. With this structure, FDSOI device parameter degradation due to total dose is studied, and some abnormal phenomena, such as the transconductance hump and the mobility enhancement, are observed and discussed. Sentaurus TCAD simulations are used for further analysis. Moreover, the impact of negative back-gate bias to transistor parameter degradation is investigated, and an improved back-gate compensation strategy is proposed. Technology improvement such as thinning the BOX on total ionizing dose (TID) amelioration is also discussed with TCAD simulation.

New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs

Abstract: Anomalous transconductance with nonmono- tonic back-gate bias dependence observed in the fully depleted silicon-on-insulator (FDSOI) MOSFET with thick front-gate oxide is discussed. It is found that the anomalous transconductance is attributed to the domination of the back-channel charge in the total channel charge. This behavior is modeled with a novel two-mobility model, which separates the mobility of the front and back channels. These two mobilities are physically related by a charge-based weighting function. The proposed model is incorporated into BSIM-IMG and is in good agreement with the experimental and simulated data of FDSOI MOSFETs for various front-gate oxides, body thicknesses, and gate lengths.

Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis

Abstract: This paper discusses in detail the effects of Sub-10nm fin-width ( $\text{W}_{fin}$ ) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the trans-conductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm $\text{W}_{fin}$ regime, cannot be improved just by $\text{W}_{fin}$ scaling but by optimizing source/drain resistance, gate dielectric thickness together with the $\text{W}_{fin}$ scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.

Compact Modeling of Advanced CMOS and Emerging Devices for Circuit Simulation

Abstract: Author(s): Lin, Yen-Kai | Advisor(s): Hu, Chenming | Abstract: Compact model plays an important role in designing integrated circuits and serves as a bridge to share the information between foundries and circuit designers. Since various flavors of transistor architectures like FDSOIs and FinFETs are proposed to improve device performances, the accurate, fast, and robust compact models, which are capable of reproducing the very complicated transistor characteristics like transconductance, are urgently required. Novel device concept, such as tunnel FETs (TFETs) and negative capacitance FETs (NCFETs), needs new device modeling methodology and understanding of device physics. In addition to transistors, memory device like magnetic tunnel junction (MTJ) compact model is also crucial for circuit designs. This dissertation presented the advanced research on compact models for the state-of-the art transistor and memory technologies: FDSOIs, FinFETs, TFETs, NCFETs, and MTJs.Due to the limitations in the aggressively scaled planar transistors, the devices with good electrostatic control are discussed and modeled into the industry standard model - BSIM-IMG for FDSOIs and BSIM-CMG for multi-gate FETs. Although the dynamic back-gate bias change help reduce the static power in FDSOIs, the leakages, overlap capacitance, and carrier transport are thus showing back-gate bias-dependence. The enhanced gate-related leakage, overlap capacitance, and mobility compact models are validated against the silicon data and incorporated into BSIM-IMG. The leakages through subsurface path and source-to-drain direct tunneling due to extremely short channel are also included in this work, which are in excellent agreement with the technology computer-aided design (TCAD) and atomistic simulations. The computationally efficiency of these models are the key solutions for evaluating the circuit performance of future technology nodes.Two paradigms of steep subthreshold slope transistors - TFETs and NCFETs as the promising candidates for future Internet of Things (IoT) and logic/analog applications are also presented in this thesis. TFET has a gated p-i-n diode structure, where the current relies on direct band-to-band tunneling in source/channel junction. Such tunneling mechanism breaks the tradition limitation of MOSFET turn-ON characteristics called the Boltzmann tyranny. The improvements in power consumption and delay of circuits are thus the emphasis and attention of device community, where the need of TFET compact model is fulfilled with the developed model in this work. NCFET is rapidly emerging as a preferred replacement for traditional MOSFET since the recent discovery of ferroelectric (FE) materials to amplify the voltage suggests that further scaling supply voltage is possible with the CMOS-compatible fabrication process of NCFET. The short channel effect, ferroelectric variability, and spacer optimization design are the focus in this thesis. The compact model of NCFET is improved to be more predictive for ferroelectric properties with verification against TCAD simulations. Monte-Carlo method is carried out in FE variability study, where the main finding is that the dielectric phase is critical but fortunately is theoretically possible to be absent. The spacer design reveals that further engineering the capacitance matching via parasitic capacitance is the key solution for future technology nodes.In addition to transistor compact models and physics, the memory device - spin-transfer-torque magnetic tunnel junction (STT-MTJ) is also presented. The resistances and critical currents are derived from the Landau-Lifshitz-Gilbert (LLG) equation and modeled analytically. The RC sub-circuit is found to describe the dynamic switching behavior of MTJ due to the precession and thermal fluctuation. The proposed MTJ compact model has been validated with silicon data from the industry and is capable of simulating a memory circuit with previously mentioned BSIM models.

Operation and modeling of the MOS transistor

Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

A review of recent MOSFET threshold voltage extraction methods

Abstract: The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted from either measured drain current or capacitance characteristics, using a single or more transistors. Practical circuits based on some of the most common methods are available to automatically and quickly measure the threshold voltage. This article reviews and assesses several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics. The assessment focuses specially on single-crystal bulk MOSFETs. It includes 11 different methods that use the transfer characteristics measured under linear regime operation conditions. Additionally two methods for threshold voltage extraction under saturation conditions and one specifically suitable for non-crystalline thin film MOSFETs are also included. Practical implementation of the several methods presented is illustrated and their performances are compared under the same challenging conditions: the measured characteristics of an enhancement-mode n-channel single-crystal silicon bulk MOSFET with state-of-the-art short-channel length, and an experimental n-channel a-Si:H thin film MOSFET. 2002 Elsevier Science Ltd. All rights reserved.

An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode

Abstract: In this paper, we report an experimental investigation of electron mobility in ultrathin SOI MOSFETs operated in double-gate mode. Mobility is measured for silicon thickness down to approximately 5 nm and for different temperatures. Mobility data in single- and double-gate mode are then compared according to two different criteria imposing either the same total inversion charge density or the same effective field in the two operating modes. Our results demonstrate that for silicon films around 10 nm or thinner and at small inversion densities, a modest but unambiguous mobility improvement for double-gate mode operation is observed even if the same effective field as in the single-gate mode is kept. Furthermore, we also document that the mobility in double-gate mode can improve markedly above single-gate mobility when the comparison is made at the same total inversion density. This latter feature of the double-gate operating mode can be very beneficial in the perspective of very-low voltage operation.

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

Abstract: A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.