Predictive effective mobility model for FDSOI transistors using technology parameters

TL;DR: This is the first time, when a predictive mobility model for wide range of back gate biases, solely dependent on technology parameters (front and back gate oxide thickness T _ox/_{box, front/back gate bias V< sub>fg}

Abstract: by Pragya Kushwaha, Harshit Agarwal, Mandar Bhoir, Nihar R. Mohapatra, Sourabh Khandelwal, Juan Pablo Duarte, Yen-Kai Lin, Huan-Lin Chang, Chenming hu and Yogesh Singh Chauhan

TL;DR: In this article, double SOI was introduced to mitigate the radiation impact on fully depleted silicon-on-insulator (FDSOI) devices, and the impact of negative back-gate bias to transistor parameter degradation was investigated, and an improved backgate compensation strategy was proposed.

Abstract: The existence of buried oxide (BOX) layer and the strong coupling effect between the front and back channels can worsen the radiation-induced degradation on fully depleted silicon-on-insulator (FDSOI) device. To mitigate the radiation impact, a new structure named double SOI is introduced in this paper. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the BOX layer. With this structure, FDSOI device parameter degradation due to total dose is studied, and some abnormal phenomena, such as the transconductance hump and the mobility enhancement, are observed and discussed. Sentaurus TCAD simulations are used for further analysis. Moreover, the impact of negative back-gate bias to transistor parameter degradation is investigated, and an improved back-gate compensation strategy is proposed. Technology improvement such as thinning the BOX on total ionizing dose (TID) amelioration is also discussed with TCAD simulation.

TL;DR: In this paper, an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs is presented.

Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.

TL;DR: In this paper, anomalous transconductance with nonmono tonic back-gate bias dependence observed in the fully depleted silicon-on-insulator (FDSOI) MOSFET with thick front-gate oxide is discussed.

Abstract: Anomalous transconductance with nonmono- tonic back-gate bias dependence observed in the fully depleted silicon-on-insulator (FDSOI) MOSFET with thick front-gate oxide is discussed. It is found that the anomalous transconductance is attributed to the domination of the back-channel charge in the total channel charge. This behavior is modeled with a novel two-mobility model, which separates the mobility of the front and back channels. These two mobilities are physically related by a charge-based weighting function. The proposed model is incorporated into BSIM-IMG and is in good agreement with the experimental and simulated data of FDSOI MOSFETs for various front-gate oxides, body thicknesses, and gate lengths.

TL;DR: In this paper, the effects of sub-10nm fin-width scaling on the analog performance and variability of FinFETs have been investigated and a systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.

Abstract: This paper discusses in detail the effects of Sub-10nm fin-width ( $\text{W}_{fin}$ ) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the trans-conductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm $\text{W}_{fin}$ regime, cannot be improved just by $\text{W}_{fin}$ scaling but by optimizing source/drain resistance, gate dielectric thickness together with the $\text{W}_{fin}$ scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.

TL;DR: It is reported that the thin BOX along with higher ground-plane (GP) doping will limit the electron/hole mobility of ultrathin body and BOX fully depleted silicon-on-insulator (UTBB FD-SOI) MOS transistors.

Abstract: In this article, the combined effect of BOX thickness ( ${T}_{\text {BOX}}$ ) and ground-plane (GP) doping ( ${N}_{\text {GP}}$ ) on channel carrier mobility and analog figures of merit (FoMs) is investigated It is reported that the thin BOX along with higher ${N}_{\text {GP}}$ will limit the electron/hole mobility of ultrathin body and BOX fully depleted silicon-on-insulator (UTBB FD-SOI) MOS transistors The physics responsible for this observation is discussed in detail The contrasting behavior of different GPs, the effect of ${T}_{\text {BOX}}$ scaling, and gate-length scaling on device behavior is also analyzed It is also shown that in advanced UTBB FD-SOI MOS transistors, a tradeoff exists between transistor intrinsic gain, cutoff frequency, and non-linearity In nMOS transistors, the best intrinsic gain and cut-off frequency can be achieved with ultrathin BOX and n-type GP (or with no GP), whereas the best linearity can be achieved with ultrathin BOX and p-type GP implant

TL;DR: In this article, a simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described, based on the linear relationship between the intrinsic gate capacitance and effective channel length.

Abstract: A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.

TL;DR: For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated and the effectiveness of back biasing for short devices in order to achieve I-ON current improvement by 45% for LVT options at an I-OFF current of 23nA/µm and a leakage reduction by 2 decades.

Abstract: For the first time, Multi-V T UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve I ON current improvement by 45% for LVT options at an I OFF current of 23nA/µm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um2 bitcells with 290mV SNM at 1.1V and Vb=0V operation were obtained. We also demonstrate on ring oscillators and 0.299µm2 SRAM bitcells the effectiveness (ΔV T versus V b ∼ 208mV/V) of the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances.

TL;DR: Based on the physics of scattering mechanisms of MOSFET inversion layer carriers at different temperatures and vertical electric fields, a new unified mobility model of wide temperature (77 - 400 K) and range is proposed for IC simulation as mentioned in this paper.

Abstract: Based on the physics of scattering mechanisms of MOSFET inversion layer carriers at different temperatures and vertical electric fields, a new unified mobility model of wide temperature (77 - 400 K) and range is proposed for IC simulation. Measurement data taken in a wide range of temperatures and electric fields are compared with the simulation results of a MOSFET current model implementing this new mobility equation. Excellent agreement between the simulation and measurement data is found.

TL;DR: In this paper, the authors modified the standard MOSFET definition for effective electric field for SOI devices to account for nonzero electric field at the back oxide interface and showed that the effective channel mobility in fully-depleted n-channel SOI MOSDFET's is independent of applied backgate bias when the modified E/sub eff/ definition is used.

Abstract: The standard bulk MOSFET definition for effective electric field is modified for SOI devices to account for nonzero electric field at the back oxide interface. The effective channel mobility in fully-depleted n-channel SOI MOSFET's is shown to be independent of applied backgate bias when the modified E/sub eff/ definition is used. The effective channel mobility as a function of E/sub eff/ is also shown to be independent of film thickness for fully-depleted devices. >

TL;DR: In this paper, the channel width and gate-oxide thickness of conventional and LDD MOSFETs are determined based on the linear relationship between the intrinsic gate capacitance and effective channel width.

Abstract: A new method to determine the channel widths and in situ gate-oxide thicknesses of conventional and LDD MOSFET's is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel width. Measurements from two gate biases on devices of different channel widths are sufficient to obtain a full characterization. Channel widths and gate-oxide thicknesses determined by this method are given for both types of devices. This method applies to large-size as well as small-size, test devices.