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Proceedings ArticleDOI

Probabilistic Error Modeling for Two-part Segmented Approximate Adders

TL;DR: This paper model the error of various two-part segmented approximate adders using probabilistic analysis and derive expressions for some basic error metrics used in literature and compares the results obtained using these expressions for various error metrics with those using Monte Carlo simulations for different input distributions.
Abstract: Approximate adders are used in applications that are error tolerant to save on power and area. We consider the class of two-part segmented approximate adders, where the upper part of the sum is computed accurately and the lower part of the sum is approximated. In this paper, we model the error of various two-part segmented approximate adders using probabilistic analysis and derive expressions for some basic error metrics used in literature. We compare the results obtained using our expressions for various error metrics with those using Monte Carlo simulations for different input distributions. Further, in an image addition application, we use our expression derived for mean square error and show that it predicts the PSNR correctly.
Citations
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Journal ArticleDOI
TL;DR: Efficient small constant mean-error imprecise adder and multiplier are developed based on a systematic mathematical-logical approach for efficient implementation of a general multiply-accumulate (MAC) block as the basic building block of many imprecision tolerant applications including digital signal processing and soft computing.
Abstract: Due to considerable effectiveness of the imprecise computing paradigm in hardware implementation of many applications, great attention has been recently paid by many research groups to develop different novel imprecise computational blocks such as adders and multipliers. Traditionally, the imprecise blocks are developed in an application independent manner, just similar to development of a conventional precise block. This article investigates the systematic application oriented development of the imprecise computational blocks which results in more customized components. The main focus is on the development of customized imprecise adder/multiplier for efficient implementation of a general multiply-accumulate (MAC) block as the basic building block of many imprecision tolerant applications including digital signal processing and soft computing. To develop some customized blocks for the MAC, the error behaviors of the suitable imprecise adder and multiplier are first extracted by analyzing the MAC. Based on analysis results, efficient small constant mean-error imprecise adder and multiplier are developed based on a systematic mathematical-logical approach. A wide range of synthesis and simulation results are provided to demonstrate efficiency of custom developed imprecise blocks with respect to some of the best existing imprecise blocks in a general MAC and a real 2D-Convolution application.

11 citations


Cites methods from "Probabilistic Error Modeling for Tw..."

  • ...on the proposed approach, we first provide an analytical proof to support the structure of the LOA imprecise adder as one of the most efficient and most cited existing adders [29], [30], [31], [32], [33], [34], [35], [36]....

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  • ...Exploiting a systematicmathematical-logical approach to support hardware structure of the small constant mean error LOA adder as one of the most efficient existing imprecise adders [29], [30], [31], [32], [33], [34], [35], [36], [37]....

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Journal ArticleDOI
TL;DR: Synthesis results, accuracy analysis, and evaluation in two commonly used error-tolerant applications demonstrate the superiority of the proposed architectures over the state-of-the-art DA-based approximate structures.
Abstract: Distributed arithmetic (DA)-based approximate structures are used for efficient implementation of inner-products in various error-resilient applications. In the existing literature, most of these approximate architectures are developed by truncating the least significant bits (LSBs) of the inputs and/or the multiplying coefficients. The existing works do not provide any analytical study to evaluate and design an approximate structure. To address this issue, an analytical framework is proposed in this paper. It is shown that the analytical results match very closely with the Monte Carlo simulation results. The proposed framework reveals that the truncation of the LSBs of partial inner-products is a promising alternative to design more efficient DA architectures with less error. Following these observations, a novel approach to truncate the LSBs of partial inner-products, namely, a weight-dependent truncation strategy and its two variants with a suitable error compensation function are presented in this paper. Synthesis results, accuracy analysis, and evaluation in two commonly used error-tolerant applications demonstrate the superiority of the proposed architectures over the state-of-the-art DA-based approximate structures.

8 citations


Cites methods from "Probabilistic Error Modeling for Tw..."

  • ...Error metrics such as mean error distance (MED) and mean square error (MSE) are commonly used for the evaluation of approximate circuits [16]....

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Journal ArticleDOI
TL;DR: This paper analyzes the logic operations of the state-of-the-art adders and presents a novel low complexity adder segment with new carry prediction logic by removing the redundant logic and sharing the common operations.
Abstract: The compute-intensive multimedia applications on portable devices require power and area efficient arithmetic units. The adder is a prime building block of these arithmetic units and limits the overall performance. Therefore, this paper analyzes the logic operations of the state-of-the-art adders and presents a novel low complexity adder segment with new carry prediction logic by removing the redundant logic and sharing the common operations. Further, a new power and area efficient approximate carry skip PAEA-CSK adder is proposed using the novel adder segment. The effectiveness of the proposed PAEA-CSK adder is evaluated and compared over the existing adders by implementing them in VHDL and synthesizing using the Synopsys Design Compiler with the 65nm TSMC CMOS Library. The synthesis result shows that the proposed PAEA-CSK adder requires 27.28% and 18.03% less area and power, respectively, over the existing carry skip-based approximate adder with the same accuracy. Further, the Sobel edge detector SED embedded with the proposed adder improves PSNR by a minimum of 16.94 dB over the SED embedded with a nonzeroing bit-truncation adder.

2 citations


Cites background from "Probabilistic Error Modeling for Tw..."

  • ...Further, the probabilistic error analysis of these segment-based adders is presented in [20, 21]....

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Posted Content
TL;DR: A significant improvement of accuracy in the prediction of the noise power of DSP systems containing approximate adders and parameterized error models are derived that can be used within any optimization framework in order to optimize the number of approximate bits.
Abstract: Approximate circuit design has gained significance in recent years targeting error tolerant applications. In this paper, we first demonstrate that the commonly used assumption that the inputs to the adder are uniformly distributed results in an inaccurate prediction of error statistics for multi-level circuits. To overcome this problem, we derive parameterized error models that can be used within any optimization framework in order to optimize the number of approximate bits. We also show that in order to accurately compute the mean square error, the optimization framework needs to take into account not just the functionality of the adder, but also its position in the circuit, functionality of its parents and the number of approximate bits in the parent blocks. We demonstrate a significant improvement of accuracy in the prediction of the noise power of DSP systems containing approximate adders.

1 citations


Cites methods from "Probabilistic Error Modeling for Tw..."

  • ...Its error metrics are derived in our earlier work [16]....

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Journal ArticleDOI
TL;DR: An efficient BCNN deployment method is proposed, including a quality-circuit co-design method for approximate adder generation, aquality-aware intercompensation approach for addition tree, and a computing quality involved retraining approach forBCNN deployment.
Abstract: As the artificial intelligence and Internet of Things (AIoT) develop rapidly, the deployment of artificial neural networks in edge computing is becoming significant with great challenge. The binarized convolutional neural network (BCNN) is one of the most widely adopted light-weight ANNs in AIoT, which can achieve the balance of system accuracy and hardware resource consumption, compared to others. To achieve high power and area efficiency in BCNN deployment, many approximate computing (AxC) techniques are integrated to make full use of the resilience of BCNN. As the research focused on the integration of AxC in circuit design, the design of AxC itself is not fully considered when applied to specific applications or domains. Based on circuit-architecture-system co-design, this article proposes an efficient BCNN deployment method, including a quality-circuit co-design method for approximate adder generation, a quality-aware intercompensation approach for addition tree, and a computing quality involved retraining approach for BCNN deployment. Experimental results show that the proposed quality model can achieve 86.43% in average accuracy while evaluating nine types of typical approximate adders. The proposed method is conducted on the applications of keyword spotting of GSCD, MNIST, and CIFAR-10, and we can further rise the approximation degree by 50%–75%, while reducing the accuracy by less than 1%.

1 citations

References
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Proceedings ArticleDOI
27 May 2013
TL;DR: This paper reviews recent progress in the area, including design of approximate arithmetic blocks, pertinent error and quality measures, and algorithm-level techniques for approximate computing.
Abstract: Approximate computing has recently emerged as a promising approach to energy-efficient design of digital systems. Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality or optimality in the computed result. By relaxing the need for fully precise or completely deterministic operations, approximate computing techniques allow substantially improved energy efficiency. This paper reviews recent progress in the area, including design of approximate arithmetic blocks, pertinent error and quality measures, and algorithm-level techniques for approximate computing.

921 citations

Journal ArticleDOI
TL;DR: This paper proposes logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates the utility of these approximate adders in two digital signal processing architectures with specific quality constraints.
Abstract: Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.

637 citations


"Probabilistic Error Modeling for Tw..." refers background or methods in this paper

  • ...MSEama5 = Pk−12 2(k−1) + k−2∑ i=0 Pi2 2i + k−2∑ i=0 k−2∑ j=0,j 6=i Pij2 i+j − 2kPk−1 k−2∑ i=0 Pi2 i (16) MSEloa = k−2∑ i=0 P 2i 2 2i + k−2∑ i=0 k−2∑ j=0,j 6=i P 2ij2 i+j + P 2k−12 2(k−1) − 2kP 2k−1 k−2∑ i=0 P 2i 2 i. (17) Thus, we see that MSE of truncation, AMA5 and LOA depends only on Pi and the joint probability Pij ....

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  • ...From the description in the previous section, for Truncation, LOA and AMA5 adders, ck−1, SL = {0, 0}, Truncation {ak−1&bk−1, ak−1:0||bk−1:0},LOA {ak−1, bk−1:0}, AMA5 (1) For the ETA, ck−1 = 0....

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  • ...In the approximate mirror adder 5 (AMA5) proposed in [4], the lower part of the result is set as SL = AL and the carry is set as ck−1 = bk−1....

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  • ...Approximate logic is used to compute the lower part of the sum containing the remaining least significant bits (LSBs) [4], [5], [6], [7]....

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  • ...Although [4] contains a detailed derivation of the mean error for uniformly distributed inputs, there are no expressions for either MSE or MED....

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Journal ArticleDOI
TL;DR: It is shown that these proposed Bio-inspired Imprecise Computational blocks (BICs) can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.
Abstract: The conventional digital hardware computational blocks with different structures are designed to compute the precise results of the assigned calculations. The main contribution of our proposed Bio-inspired Imprecise Computational blocks (BICs) is that they are designed to provide an applicable estimation of the result instead of its precise value at a lower cost. These novel structures are more efficient in terms of area, speed, and power consumption with respect to their precise rivals. Complete descriptions of sample BIC adder and multiplier structures as well as their error behaviors and synthesis results are introduced in this paper. It is then shown that these BIC structures can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.

458 citations


"Probabilistic Error Modeling for Tw..." refers background or methods in this paper

  • ...Among the considered two-part segmented adders, LOA and ETA have the least MED, which is approximately one-fifth that of truncation adder....

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  • ...MED of LOA is given by MEDloa = (1− P 2k−1) k−2∑ i=0 P 2i 2 i + P 2k−1 ( 2k−1 − k−2∑ i=0 P 2i 2 i ) = (1− 2P 2k−1) k−2∑ i=0 P 2i 2 i + P 2k−12 k−1....

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  • ...MSEama5 = Pk−12 2(k−1) + k−2∑ i=0 Pi2 2i + k−2∑ i=0 k−2∑ j=0,j 6=i Pij2 i+j − 2kPk−1 k−2∑ i=0 Pi2 i (16) MSEloa = k−2∑ i=0 P 2i 2 2i + k−2∑ i=0 k−2∑ j=0,j 6=i P 2ij2 i+j + P 2k−12 2(k−1) − 2kP 2k−1 k−2∑ i=0 P 2i 2 i. (17) Thus, we see that MSE of truncation, AMA5 and LOA depends only on Pi and the joint probability Pij ....

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  • ...(13) Using (6), the error distance of LOA is given by edloa = k−2∑ i=0 (ai&bi)2 i, ak−1&bk−1 = 0 2k−1 − k−2∑ i=0 (ai&bi)2 i, ak−1&bk−1 = 1....

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  • ...For the LOA, the authors have included an expression for MSE in [5] assuming uniformly distributed inputs, but it is not clear how it was derived....

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Journal ArticleDOI
TL;DR: New metrics are proposed for evaluating the reliability as well as the power efficiency of approximate and probabilistic adders and it is shown that the MED is an effective metric for measuring the implementation accuracy of a multiple-bit adder and that the NED is a nearly invariant metric independent of the size of an adder.
Abstract: Addition is a fundamental function in arithmetic operation; several adder designs have been proposed for implementations in inexact computing. These adders show different operational profiles; some of them are approximate in nature while others rely on probabilistic features of nanoscale circuits. However, there has been a lack of appropriate metrics to evaluate the efficacy of various inexact designs. In this paper, new metrics are proposed for evaluating the reliability as well as the power efficiency of approximate and probabilistic adders. Reliability is analyzed using the so-called sequential probability transition matrices (SPTMs). Error distance (ED) is initially defined as the arithmetic distance between an erroneous output and the correct output for a given input. The mean error distance (MED) and normalized error distance (NED) are then proposed as unified figures that consider the averaging effect of multiple inputs and the normalization of multiple-bit adders. It is shown that the MED is an effective metric for measuring the implementation accuracy of a multiple-bit adder and that the NED is a nearly invariant metric independent of the size of an adder. The MED is, therefore, useful in assessing the effectiveness of an approximate or probabilistic adder implementation, while the NED is useful in characterizing the reliability of a specific design. Since inexact adders are often used for saving power, the product of power and NED is further utilized for evaluating the tradeoffs between power consumption and precision. Although illustrated using adders, the proposed metrics are potentially useful in assessing other arithmetic circuit designs for applications of inexact computing.

453 citations


"Probabilistic Error Modeling for Tw..." refers background in this paper

  • ...The two metrics that are used most often to evaluate these adders are MED and MSE [16], [17], [9]....

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  • ...We derive expressions for mean error, MED and MSE....

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  • ...We assume both the inputs A and B to be independent and identically distributed (i.i.d.) and derive expressions for mean error, MED and MSE....

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  • ...Metrics The two metrics that are used most often to evaluate these adders are MED and MSE [16], [17], [9]....

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Proceedings ArticleDOI
03 Jun 2012
TL;DR: This paper proposes an accuracy-configurable approximate adder for which the accuracy of results is configurable during runtime, and can be used in accuracy- configurable applications, and improves the achievable tradeoff between performance/power and quality.
Abstract: Approximation can increase performance or reduce power consumption with a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic can be used to generate sufficient results rather than absolutely accurate results. Approximate design exploits a tradeoff of accuracy in computation versus performance and power. However, required accuracy varies according to applications, and 100% accurate results are still required in some situations. In this paper, we propose an accuracy-configurable approximate (ACA) adder for which the accuracy of results is configurable during runtime. Because of its configurability, the ACA adder can adaptively operate in both approximate (inaccurate) mode and accurate mode. The proposed adder can achieve significant throughput improvement and total power reduction over conventional adder designs. It can be used in accuracy-configurable applications, and improves the achievable tradeoff between performance/power and quality. The ACA adder achieves approximately 30% power reduction versus the conventional pipelined adder at the relaxed accuracy requirement.

385 citations


"Probabilistic Error Modeling for Tw..." refers background in this paper

  • ...There are other approximate adders [8], [9], [10], [11] which do not split the output into approximate lower part and accurate upper part....

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  • ...Metrics The two metrics that are used most often to evaluate these adders are MED and MSE [16], [17], [9]....

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