Process and Temperature Compensation in a 7-MHz
01 Jan 2006-
TL;DR: In this article, the design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25-m, two-poly five-metal (2P5M) CMOS process is described.
Abstract: This paper reports on the design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25- m, two-poly five-metal (2P5M) CMOS process. Measurements made across a temperature range of 40 C to 125 C and 94 samples collected over four fabrica- tion runs indicate a worst case combined variation of 2.6% (with process, temperature and supply). No trimming was performed on any of these samples. The oscillation frequencies of 95% of the sam- ples were found to fall within 0.5% of the mean frequency and the standard deviation was 9.3 kHz. The variation of frequency with power supply was 0.31% for a supply voltage range of 2.4-2.75 V. The clock generator is based on a three-stage differential ring oscillator. The variation of the frequency of the oscillator with tem- perature and process has been discussed and an adaptive biasing scheme incorporating a unique combination of a process corner sensing scheme and a temperature compensating network is de- veloped. The biasing circuit changes the control voltage of the dif- ferential ring oscillator to maintain a constant frequency. A com- parator included at the output stage ensures rail-to-rail swing. The oscillator is intended to serve as a start-up clock for micro-con- troller applications.
Citations
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TL;DR: A long-range UHF RF identification (RFID) sensor has been designed using a 0.35- ¿m CMOS standard process that allows the use of the RFID as a batteryless sensor in a wireless human body temperature monitoring system.
Abstract: A long-range UHF RF identification (RFID) sensor has been designed using a 0.35- ?m CMOS standard process. The power-optimized tag, combined with the ultralow-power temperature sensor, allows an ID and a temperature reading range of 2 m from a 2-W effective radiated power output power reader. The temperature sensor is based on a ring oscillator, where the temperature dependence of the oscillation frequency is used for thermal sensing. The temperature sensor exhibits a resolution of 0.035°C and an inaccuracy value lower than 0.1°C in the range from 35°C to 45°C after two-point calibration. The average power consumption of the temperature sensor is only 110 nW at ten conversions per second while keeping a high resolution and accuracy. These properties allow the use of the RFID as a batteryless sensor in a wireless human body temperature monitoring system.
220 citations
TL;DR: An on-chip CMOS relaxation oscillator with voltage averaging feedback using a reference proportional to supply voltage is presented and achieves 7x reduction in accumulated jitter (at 1500th cycle) as compared to a oscillator without VAF.
Abstract: An on-chip CMOS relaxation oscillator with voltage averaging feedback using a reference proportional to supply voltage is presented. A voltage-averaging feedback (VAF) concept is proposed to overcome conventional relaxation oscillator problems such as sensitivity to comparator delay, aging, and flicker noise of current sources. A test-chip with typical frequency of 14.0 MHz was fabricated in a 0.18 μm standard CMOS process and measured frequency variations of ±0.16 % for supply changes from 1.7 to 1.9 V and ±0.19% for temperature changes from -40 to 125°C. The prototype draws 25 μA from a 1.8 V supply, occupies 0.04 mm2, and achieves 7x reduction in accumulated jitter (at 1500th cycle) as compared to a oscillator without VAF.
179 citations
04 Oct 2010
TL;DR: This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band and proposes a dual-path clock generator to support both applications with either very accurate link frequency or very low power consumption.
Abstract: This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band. A dual-path clock generator is proposed to support both applications with either very accurate link frequency or very low power consumption. On-chip temperature sensing is accomplished with a time-readout scheme to reduce the power consumption. Moreover, a gain-compensation technique is proposed to reduce the temperature sensing error due to process variations by using the same bandgap reference of the tag to generate bias currents for both the current-to-digital converter and the clock generator of the sensor. Also integrated is a 128-bit one-time-programmable (OTP) memory array based on gate-oxide antifuse without extra mask steps. Fabricated in a standard 0.18- μm CMOS process with analog options, the 1.1-mm2 tag chip is bonded onto an antenna using flip-chip technology to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. The tag inlay achieves a sensitivity of -6 dBm and a sensing inaccuracy of ±0.8° C (3 σ inaccuracy) over operating temperature range from -20°C to 30°C with one-point calibration.
172 citations
TL;DR: The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented, making it suitable for application in wireless sensor networks (WSN) and less than 1.1% over the temperature range from -22degC to 85degC.
Abstract: The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3sigma) over the temperature range from -22degC to 85degC . Fabricated in a baseline 65 nm CMOS technology, the frequency reference circuit occupies 0.11 mm2 and draws 34 muA from a 1.2 V supply at room temperature.
90 citations
TL;DR: A fully-integrated 18.5 kHz RC time-constant-based oscillator is designed in 65 nm CMOS for sleep-mode timers in wireless sensors and provides timing noise suppression, leading to 10× reduction in long-term Allan deviation.
Abstract: A fully-integrated 18.5 kHz RC time-constant-based oscillator is designed in 65 nm CMOS for sleep-mode timers in wireless sensors. A comparator offset cancellation scheme achieves $4\times $ to $25\times $ temperature stability improvement, leading to an accuracy of ±0.18% to ±0.55% over −40 to 90 °C. Sub-threshold operation and low-swing oscillations result in ultra-low power consumption of 130 nW. The architecture also provides timing noise suppression, leading to $10\times $ reduction in long-term Allan deviation. It is measured to have a stability of 20 ppm or better for measurement intervals over 0.5 s. The oscillator also has a fast startup-time, with the period settling in 4 cycles.
84 citations
References
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Book•
01 Jan 1977
TL;DR: In this article, the authors combine bipolar, CMOS and BiCMOS analog integrated circuits into a unified treatment that stresses their commonalities and highlights their differences, and provide valuable insights into the relative strengths and weaknesses of these important technologies.
Abstract: The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.
4,717 citations
Book•
01 Jan 1987
TL;DR: In this article, the authors present a simple MOS LARGE-SIGNAL MODEL (SPICE Level 1) and a small-signal model for the MOS TRANSISTOR.
Abstract: 1.1 ANALOG INTEGRATED CIRCUIT DESIGN 1.2 NOTATION, SYMBOLOGY AND TERMINOLOGY 1.3 ANALOG SIGNAL PROCESSING 1.4 EXAMPLE OF ANALOG VLSI MIXED-SIGNAL CIRCUIT DESIGN 2.1 BASIC MOS SEMICONDUCTOR FABRICATION PROCESSES 2.2 THE PN JUNCTION 2.3 THE MOS TRANSISTOR 2.4 PASSIVE COMPONENTS 2.5 OTHER CONSIDERATIONS OF CMOS TECHNOLOGY 3.1 SIMPLE MOS LARGE-SIGNAL MODEL (SPICE LEVEL 1) 3.2 OTHER MOS LARGE-SIGNAL MODEL PARAMETERS 3.3 SMALL-SIGNAL MODEL FOR THE MOS TRANSISTOR 3.4 COMPUTER SIMULATION MODELS 3.5 SUBTHRESHOLD MOS MODEL 3.6 SPICE SIMULATION OF MOS CIRCUITS 4.1 MOS SWITCH 4.2 MOS DIODE/ACTIVE RESISTOR 4.3 CURRENT SINKS AND SOURCES 4.4 CURRENT MIRRORS 4.5 CURRENT AND VOLTAGE REFERENCES 4.6 BANDGAP REFERENCE 5.1 INVERTERS 5.2 DIFFERENTIAL AMPLIFIERS 5.3 CASCODE AMPLIFIERS 5.4* CURRENT AMPLIFIERS 5.5* OUTPUT AMPLIFIERS/BUFFERS 6.1 DESIGN OF CMOS OP AMPS 6.2 COMPENSATION OF OP AMP 6.3 DESIGN OF TWO-STAGE OP AMPS 6.4 POWER-SUPPLY REJECTION RATIO OF TWO-STAGE OP AMPS 6.5 CASCODE OP AMPS 6.6 SIMULATION AND MEASUREMENT OF OP AMPS 6.7 MACROMODELS FOR OP AMPS 7.1 BUFFERED OP AMPS 7.2 HIGH-SPEED/FREQUENCY OP AMPS 7.3 DIFFERENTIAL-OUTPUT OP AMPS 7.4 MICROPOWER OP AMPS 7.5 LOW NOISE OP AMPS 7.6 LOW VOLTAGE OP AMPS 8.1 CHARACTERIZATION OF A COMPARATOR 8.2 TWO-STAGE, OPEN-LOOP COMPARATOR DESIGN 8.3 OTHER OPEN-LOOP COMPARATORS 8.4 IMPROVING THE PERFORMANCE OF OPEN-LOOP COMPARATORS 8.5 DISCRETE-TIME COMPARATORS 8.6 HIGH-SPEED COMPARATORS APPENDIX A CIRCUIT ANALYSIS FOR ANALOG CIRCUIT DESIGN APPENDIX B INTEGRATED CIRCUIT LAYOUT APPENDIX C CMOS DEVICE CHARACTERIZATION APPENDIX D TIME AND FREQUENCY DOMAIN RELATIONSHIP FOR SECOND-ORDER SYSTEMS
2,741 citations
Book•
01 Jan 1996
TL;DR: Semiconductor Models -- A General Introduction, Field Effect Introduction -- the J-FET and MESFET, and Electrostatics -- Mostly Qualitative Formulation.
Abstract: I. SEMICONDUCTOR FUNDAMENTALS. 1. Semiconductors -- A General Introduction. General Material Properties. Crystal Structure. Crystal Growth. 2. Carrier Modeling. The Quantization Concept. Semiconductor Models. Carrier Properties. State and Carrier Distributions. Equilibrium Carrier Concentrations. 3. Carrier Action. Drift. Diffusion. Recombination -- Generation. Equations of State. Supplemental Concepts. 4. Basics of Device Fabrication. Fabrication Processes. Device Fabrication Examples. R1. Part I Supplement and Review. Alternative/Supplemental Reading List. Figure Sources/Cited References. Review List of Terms. Part I Review Problem Sets and Answers. IIA. PN JUNCTION DIODES. 5. PN Junction Electrostatics. Preliminaries. Quantitative Electrostatic Relationships. 6. PN Junction Diode -- I-V Characteristics. The Ideal Diode Equation. Deviations from the Ideal. Special Considerations. 7. PN Junction Diode -- Small-Signal Admittance. Introduction. Reverse-Bias Junction Capacitance. Forward-Bias Diffusion Admittance. 8. PN Junction Diode -- Transient Response. Turn-Off Transient. Turn-On Transient. 9. Optoelectronic Diodes. Introduction. Photodiodes. Solar Cells. LEDs. IIB. BJTS AND OTHER JUNCTION DEVICES. 10. BJT Fundamentals. Terminology. Fabrication. Electrostatics. Introductory Operational Considerations. Performance Parameters. 11. BJT Static Characteristics. Ideal Transistor Analysis. Deviations from the Ideal. Modern BJT Structures. 12. BJT Dynamic Response Modeling. Equivalent Circuits. Transient (Switching) Response. 13. PNPN Devices. Silicon Controlled Rectifier (SCR). SCR Operational Theory. Practical Turn-on/Turn-off Considerations. Other PNPN Devices. 14. MS Contacts and Schottky Diodes. Ideal MS Contacts. Schottky Diode. Practical Contact Considerations. R2. Part II Supplement and Review. Alternative/Supplemental Reading List. Figure Sources/Cited References. Review List of Terms. Part II Review Problem Sets and Answers. III. FIELD EFFECT DEVICES. 15. Field Effect Introduction -- the J-FET and MESFET. General Introduction. J-FET. MESFET. 16. MOS Fundamentals. Ideal Structure Definition. Electrostatics -- Mostly Qualitative. Electrostatics -- Quantitative Formulation. Capacitance-Voltage Characteristics. 17. MOSFETs -- The Essentials. Qualitative Theory of Operation. Quantitative ID - VD Relationships. ac Response. 18. Nonideal MOS. Metal-Semiconductor Workfunction Difference. Oxide Charges. MOSFET Threshold Considerations. 19. Modern FET Structures. Small Dimension Effects. Select Structure Survey. R3. Part III Supplement and Review. Alternative/Supplemental Reading List. Figure Sources/Cited References. Review List of Terms. Part III Review Problem Sets and Answers. Appendix A. Elements of Quantum Mechanics. Appendix B. MOS Semiconductor Electrostatics -- Exact Solution. Appendix C. MOS C-V Supplement. Appendix D. MOS I-Vsupplement. Appendix E. List of Symbols. Appendix M. MATLAB Program Script.
1,048 citations
01 Nov 1996
TL;DR: In this article, a delay-locked loop (DLL) and phase-locked loops (PLL) designs based upon self-biased techniques are presented, which achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and low input tracking jitter.
Abstract: Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-/spl mu/m N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise.
1,006 citations
01 Jan 1996
763 citations