Patent•
Process for PECVD of silicon oxide using TEOS decomposition
26 Oct 1988-
TL;DR: In this article, a high pressure, high throughput, single wafer, semiconductor processing reactor is described which is capable of thermal CVD, plasma-enhanced CVD and plasma assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing.
Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.
Citations
More filters
Patent•
17 Mar 2009
TL;DR: The 3Dimensional Structure (3DS) Memory (100) as mentioned in this paper is a three-dimensional structure (3D) memory that allows physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized.
Abstract: A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
1,212 citations
Patent•
31 Mar 1994TL;DR: In this article, a chemical vapor deposition chamber (10) includes a substrate support member (18) positionable therein to receive a substrate (24) thereon for processing, and a detection system for detecting the presence of misaligned, cracked or warped substrates in the chamber.
Abstract: A chemical vapor deposition chamber (10) includes a substrate support member (18) positionable therein to receive a substrate (24) thereon for processing. The support member (18) is positioned in the chamber (10) by a moveable stem (20) which extends through a sealed aperture (100) in the base of the chamber (10). To reduce heat transfer from the stem (20) outwardly of the chamber, the stem (20) includes a heat choke portion (44). To ensure that the support member (18) does not droop or sag under the high temperature conditions present in the chamber (10), a secondary plate (91) having high thermal resistance is maintained against the non-substrate receiving side of the support member (18). The use of the secondary plate (91) enables the use of highly thermally conductive, but low thermal strength, materials for the support member (18). The chamber (10) also includes a detection system for detecting the presence of mis-aligned, cracked or warped substrates (24) in the chamber (10). The support member (18) preferably incudes a plurality of vacuum grooves (77, 78) therein, which are maintained at a vacuum pressure to firmly adhere the substrate (24) to the support member (18) during processing. If the vacuum is not maintainable in the grooves (77, 78), this is indicative of a cracked, mis-aligned or warped substrate (77, 78). If this condition occurs, a controller shuts down the chamber and indicates the presence of a cracked, warped or mis-aligned substrate (24). The chamber also provides for edge protection of the substrates (24) as they are processed in the chamber (10). This is provided by creating a purge gas channel (220) about the perimeter of the substrate (24) and aligning the edge of the substrate (24) such that a purge gas gap is provided about the perimeter of the substrate edge.
508 citations
Patent•
31 Jan 2007
TL;DR: In this article, an assembly for loading a collapsible embolic protection filter into a catheter is described, which includes an inlet end and an outlet end, the outlet end being configured for co-operative alignment with the reception space.
Abstract: An assembly for loading a collapsible embolic protection filter 1 into a catheter 2 , comprises a catheter 2 defining a reception space at a distal end of the catheter 2 for receiving a collapsed embolic protection filter 1 ; and a separate removable pushing device 8 for delivering the embolic protection filter 1 into the reception space. The pushing device 8 comprises an elongate stem 71 with a proximal stop 72 for engagement with the filter 1 . A separate loading device 7 to collapse the embolic protection filter 1 is also provided. The loading device 7 defines an inlet end and an outlet end, the outlet end being configured for co-operative alignment with the reception space.
489 citations
Patent•
16 Jun 1998Abstract: A faceplate for a showerhead of a semiconductor wafer processing system is provided. The faceplate has a plurality of gas passageways to provide a plurality of gases to the process region without commingling those gases before they reach the processing region within a reaction chamber. The showerhead includes a faceplate and a gas distribution manifold assembly. The faceplate defines a plurality of first gas holes that carry a first gas from the manifold assembly through the faceplate to the process region, and a plurality of channels that couple a plurality of second gas holes to a radial plenum that receives the second gas from the manifold assembly. The faceplate and the manifold assembly are each fabricated from a substantially solid nickel material.
484 citations
Patent•
08 Aug 2003
TL;DR: The Vertical System Integration (VSI) method as mentioned in this paper is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application.
Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.
420 citations
References
More filters
Patent•
19 Dec 1986TL;DR: In this paper, a single wafer, semiconductor processing reactor is described, which is capable of thermal CVD, plasmaenhanced CVD and plasma assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing.
Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures.
685 citations
Patent•
26 Oct 1988TL;DR: In this paper, a high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD and plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing.
Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either along or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.
347 citations
TL;DR: In this article, the decomposition of tetra-ethoxy silane in a radio frequency (1 MHz) glow discharge was studied as a function of time, total pressure, nature of background gas, partial pressure, substrate temperature, subtrate position.
83 citations
TL;DR: In this article, the plasma-enhanced deposition of oxide, nitride, transition metal, and transition metal silicide films is discussed, focusing on the chemistry occurring in the glow discharge and on the manner in which this chemistry controls the resulting film properties.
Abstract: Plasma‐enhanced chemical vapor deposition (PECVD) of thin films has generated considerable interest in recent years. Much of this interest stems from the ability of high energy electrons in rf glow discharges (plasmas) to break chemical bonds and thereby promote chemical reactions at or near room temperature. Such considerations are particularly important when depositing films onto substrates which cannot withstand high temperatures. A further advantage, however, is that the highly reactive plasma atmosphere can result in the formation of materials with unique chemical, physical, and electrical properties. In this paper, the plasma‐enhanced deposition of oxide, nitride, transition metal, and transition metal silicide films will be discussed. Emphasis will be placed upon the chemistry occurring in the glow discharge, and on the manner in which this chemistry controls the resulting film properties.
76 citations