Process Technology Variation
TL;DR: The importance of process variation in modern transistor technology is discussed, front-end variation sources are reviewed, device and circuit variation measurement techniques are presented, and recent intrinsic transistor variation performance from the literature is compared.
Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.
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TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results
558 citations
Cites background from "Process Technology Variation"
...Comparison of recent random variation (AVT) values from the literature, illustrating improvement with high-k/metal gate and undoped structures, and the relative equivalence of all fully depleted technologies [63]....
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...Small diameter nanowire devices may operate in a regime where conduction moves from the surface of the device to the center [63]....
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TL;DR: Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting as mentioned in this paper, which has been studied in the laboratory for more than 25 years.
Abstract: Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article provides defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V compounds, and other materials. Together, these processes encompass a variety of implementations, all following the same ALE principles. While the focus is on directional etching, isotropic ALE is also included. As part of this review, the authors also address the role of power pulsing as a predecessor to ALE and examine the outlook of ALE in the manufacturing of advanced semiconductor devices.
375 citations
01 Dec 2011
TL;DR: In this paper, a comprehensive 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented.
Abstract: A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.
268 citations
Cites background from "Process Technology Variation"
...The distributions of threshold-voltage (VT) in the three FinFET designs show that the overall VT variability is dramatically reduced compared to planar bulk MOSFETs [1][2], but the new variability source, fin-edge roughness, contributes considerable variability....
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...The statistical variability and reliability introduced by RDD, LER, MGG, and random ITC in nanoscale MOSFETs is becoming one of the major concerns for CMOS scaling and integration [1][2]....
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TL;DR: Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs and they are selected as the world's first industry-standard compact model for the FinFET.
Abstract: Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the world's first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.
103 citations
Cites background from "Process Technology Variation"
...Thus, random dopant fluctuation, a major contributor to device variation, is eliminated [37]....
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TL;DR: A systematic classification of approaches that increase system resilience in the presence of functional hardware (HW)-induced errors is presented, dealing with higher system abstractions, such as the (micro)architecture, the mapping, and platform software (SW).
Abstract: Nanoscale technology nodes bring reliability concerns back to the center stage of digital system design. A systematic classification of approaches that increase system resilience in the presence of functional hardware (HW)-induced errors is presented, dealing with higher system abstractions, such as the (micro)architecture, the mapping, and platform software (SW). The field is surveyed in a systematic way based on nonoverlapping categories, which add insight into the ongoing work by exposing similarities and differences. HW and SW solutions are discussed in a similar fashion so that interrelationships become apparent. The presented categories are illustrated by representative literature examples to illustrate their properties. Moreover, it is demonstrated how hybrid schemes can be decomposed into their primitive components.
103 citations
Cites background from "Process Technology Variation"
...supply voltage fluctuations) and particle strikes are some of the most prevalent causes of such concerns [Borkar 2005], [McPherson 2006], [Kuhn et al. 2011], [Aitken et al....
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...Inherent time-zero and time-dependent device variability, noise (e.g., supply voltage fluctuations), and particle strikes are some of the most prevalent causes of such concerns (Borkar 2005; McPherson 2006; Kuhn et al. 2011; Aitken et al. 2013)....
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References
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TL;DR: In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.
Abstract: The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >
3,121 citations
"Process Technology Variation" refers background in this paper
...[31], where σΔVT is plotted versus 1/ √ LeffWeff , and the slope of the resulting line is termed AVT (see Fig....
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TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Abstract: The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.
1,456 citations
"Process Technology Variation" refers methods in this paper
...Random variation analyses of static noise margin (SNM), dynamic read stability, and writability can be performed to model the Vccmin of a 6-T SRAM cell in a large cache design [27]....
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TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
Abstract: As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
1,421 citations
"Process Technology Variation" refers background in this paper
...A LTHOUGH there has been a trend in the complementary metal–oxide–semiconductor (CMOS) literature in recent years to describe process variation as a new challenge associated with advanced CMOS technologies [1], process...
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TL;DR: In this article, a simplified model of secondary ionization, avalanche breakdown and microplasma phenomena in p-n junctions was proposed, in which holes and electrons have identical properties described by four constants: generation of highest energy or Raman phonons, energy E R and mean-free-path L R ; ionization or electron-hole pair production, threshold carrier energy E i and mean free path L i.
Abstract: The phenomena of secondary ionization, avalanche breakdown and microplasma phenomena in p - n junctions are analyzed using a simplified model in which holes and electrons have identical properties described by four constants. Only two scattering processes for carriers are considered, each having two constants: generation of highest energy or Raman phonons, energy E R and mean-free-path L R ; ionization or electron-hole pair production, threshold carrier energy E i and mean-free-path L i . E R is determined from neutron scattering data; E R = 0·063 eV for Si and 0·037 eV for Ge. The other three constants are adjustable. E i and L i / L R = r are chosen to fit data on quantum yield for photons with 1 hv Q = 3−2 exp (E g +2E i −hv) 2rE R . For silicon this gives E i = 1·1 eV (which is equal to the energy gap E g ) and r = 17·5. For germanium E i is also about 1·1 eV and r = 57. The simple model predicts that the ionization coefficient α ( F ) varies with field F as (qF rE R ) exp − (E i qL R F ) which is in good agreement with data for electrons in silicon if L R is set equal to 50 A. The model predicts an energy per pair for ionization by high-energy particles of about 2·2 E i + rE R which is in good agreement with measured values. It also predicts a hot-carrier random energy of about 0·2 eV for F = 400,000 V/cm, which agrees with the spectra of hole-electron recombination in microplasmas. Thus the three adjustable constants permit fitting six pieces of experimental data in four independent experiments in spite of the fact that the intricacies of the band structure are disregarded. The effects of statistical spatial fluctuations of donor and acceptor ions are considered and it is concluded that these will be randomly distributed according to a Poisson distribution. This randomness leads to a characteristic fluctuation voltage (qF B K) 1 2 − 0·3 V for silicon where F B is the breakdown field, and the dielectric constant K = 1·04 × 10 −12 F/cm for silicon. The effect of these fluctuations is to produce local regions in a p - n junction with breakdown about 0·7 V lower than the average in uncompensated material. The fluctuations of voltage are larger by [(N d +N a ) (N d −N a )] 1 2 in compensated material. The fluctuations can increase the apparent ionization coefficient substantially. Microplasma effects are considered and it is shown that in a junction with only the Poisson fluctuations the microplasma should be stabilized by an apparent series resistance due to space charge of magnitude 1 υ max K − 10 5 Ω where υ max = (E R m ∗ ) 1 2 is the limiting drift velocity. This is much larger than the spreading resistance term of magnitude 1 μF B K − 2000 Ω . It is concluded that typical noisy microplasma phenomena are probably associated with localized structural defects probably having two characteristics: (1) they increase the effect ionization coefficient to a value greater than 10 5 cm −1 over a region less than 10 −5 cm long; (2) they have a mechanism for capturing charge which increases the field once the microplasma has formed. Small SiO 2 precipitates and dense arrays of dislocations appear to have the requisite properties. Metal precipitates in the space-charge layer produce “soft” reverse characteristics with localized currents of the form V 6±1 .
835 citations
"Process Technology Variation" refers background in this paper
...variation has always been a critical aspect of semiconductor fabrication [2]....
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TL;DR: Several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics, focusing specially on single-crystal bulk MOSFETs are reviewed.
813 citations
"Process Technology Variation" refers background or methods in this paper
...(Right) “Constant current” method [32] of VT measurement, showing the arbitrary selection of current....
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...(Left) ELR method [32] of VT measurement, showing sensitivity to external parasitic resistance Rext....
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...1) Methods for the Measurement of VT : There are a number of measurement techniques for VT [32]....
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