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Proceedings ArticleDOI

Process variation study of Ground Plane SOI MOSFET

TL;DR: In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated, and the results show that the GPS structure is more resistant against the variations when compared to the other two structures.
Abstract: In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.
Citations
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Journal ArticleDOI
TL;DR: In this paper, a dual protruded silicon dioxide in the drift region of LDMOS (DP-LDMOS) is proposed which creates new peaks in the electric field profile and an improvement of the breakdown voltage.
Abstract: Breakdown voltage and specific on-resistance are two important parameters in lateral double diffused MOSFET (LDMOS) devices. In order to have a high breakdown voltage, the electric field profile should be uniform. In this paper a dual protruded silicon dioxide in the drift region of LDMOS (DP-LDMOS) is proposed which creates new peaks in the electric field profile and an improvement of the breakdown voltage. Also, a triple P window is considered between these protruded oxides to have the balanced charge in the drift region that helps to have a higher breakdown voltage than a conventional LDMOS transistor. The simulation with two-dimensional ATLAS simulator shows that the proposed DP-LDMOS structure has a low specific on-resistance due to incorporating the protruded oxides in the drift region.

32 citations

Journal ArticleDOI
TL;DR: In this paper, a double step partial silicon on insulator (UDDS-PSOI) was proposed to enhance the breakdown voltage (BV) and output characteristics of LDMOSFETs.

26 citations

Journal ArticleDOI
TL;DR: In this article, a Si3N4 layer SOI-MOSFET (SL-SOI) was proposed, which is a nano-scale SOI MOSFet with the Si3n4 layer in the channel region.

25 citations

Proceedings ArticleDOI
01 Dec 2010
TL;DR: In this article, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations.
Abstract: In this paper, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations. The comparative study, which is performed in a 32nm standard CMOS technology, includes read static noise margin (read SNM), read current, and standby power. The structures include SOI with ground plane in substrate (SOI-GPS), SOI with ground plane in buried oxide (SOI-GPB), and SOI without ground plane (SOI-WGP). In addition, the variations of the SRAM characteristics due to channel length and thin-film thickness variations are investigated. The results show that the SOI-GPS structure is more resistant against the process variations when compared to the other two structures.

21 citations


Cites background from "Process variation study of Ground P..."

  • ...The reasons are that the threshold voltage of GPS structure is higher and the DIBL effect is weaker in this structure [9]....

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References
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Journal ArticleDOI
Kunihiro Suzuki1, S. Pidin1
TL;DR: In this article, the authors derived an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers.
Abstract: The authors derive an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers. Their model is valid for both long- and short-channel SOI MOSFETs and demonstrates the dependence of short-channel effects on the device parameters of channel-doping concentration, gate oxide, SOI, and buried-oxide thickness. It reproduces the numerical data for sub-0.1-/spl mu/m gate-length devices better than previous models.

71 citations


"Process variation study of Ground P..." refers background in this paper

  • ...It is due to the fact that in the FD SOI, the threshold voltage and consequently its sensitivity to the thinfilm thickness are proportional to the inverse of the thin-film thickness [8]....

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  • ...This is expected because DIBL is primary affected by the channel length and the thin-film thickness has a weak effect on DIBL [8]....

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Journal ArticleDOI
TL;DR: In this paper, a comparative study on the device design method of the sub-threshold slope and the threshold voltage control in fully-depleted silicon-on-insulator MOSFETs under sub-100-nm regime is presented.
Abstract: This paper presents the comparative study on the device design method of the subthreshold slope and the threshold voltage control in fully-depleted silicon-on-insulator MOSFETs under sub-100-nm regime. As for the threshold voltage adjustment method, the combination of the back gate bias and the gate work function controls is found to provide the superior short channel effects, the suppression of the threshold voltage fluctuation due to the SOI thickness variation, and the current drive improvement. As for the subthreshold slope, the importance and the necessity of buried oxide engineering are pointed out from the viewpoint of both the substrate capacitance and short-channel effects. It is shown, consequently, that the optimization of the thickness and the permittivity of buried oxides have a significant impact on the control of the subthreshold slope under sub-100-nm regime. When the gate length is less than 100 nm, the subthreshold slope has a minimum value at the buried oxide thickness of around 40 nm, irrespective of the SOI thickness. It is also shown that the reduction in the permittivity of the buried oxides under a constant buried oxide capacitance improves the subthreshold slope.

62 citations

Journal ArticleDOI
TL;DR: In this paper, the ground plane concept is used to reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs and is effective only when the distance between the GP and the drain is small as compared with the channel length.
Abstract: The ground plane (GP) concept is one of the techniques used to reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs and is effective only when the distance between the GP and the drain is small as compared with the channel length. Therefore, if the GP is placed in the substrate (GPS), the buried oxide (BOX) thickness should be kept as small as possible which, however, results in an increased subthreshold slope. As a result, for sub-100-nm channel lengths, it is not possible to achieve both reduced DIBL and steep subthreshold slope using GPS. In this brief, a new device structure with the GP BOX is proposed to overcome the aforementioned shortcomings so that a reduced DIBL as well as an improved subthreshold slope can be obtained. Two-dimensional simulation is used to understand the efficacy of the proposed method.

52 citations


"Process variation study of Ground P..." refers background or methods in this paper

  • ...2, and also the results of [1] for 50nm-100nm technologies, we can conclude that the GPS structure is more resistant against DIBL....

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  • ...In [1], the characteristics of three SOI structures in the technology range of 50-100nm have been compared....

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  • ...As a result, DIBL deteriorates with an increase in the BOX thickness [1]....

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  • ...In nano-regime as the dimensions of devices are reduced, the performance of the FD SOI MOSFET deteriorates due to short-channel effects [1]....

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  • ...This structure has several advantages such as low electric field, high conductance, best control of shortchannel effects, and very good subthreshold slope characteristics [1]....

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Proceedings ArticleDOI
Numata1, Uchida1, Koga1, Takagi1
07 Oct 2002
TL;DR: In this article, the authors quantitatively studied device design issues regarding threshold voltage (V/sub th/) control, short channel effects (SCE) and sub-threshold slope (SS) for fully depleted (FD) SOI MOSFETs under the sub-100 nm regime.
Abstract: Device design issues regarding threshold voltage (V/sub th/) control, short channel effects (SCE) and subthreshold slope are quantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (V/sub g2/) and gate work function (/spl Phi//sub m/) control is found to provide superior SCE, V/sub th/ fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.

44 citations


"Process variation study of Ground P..." refers background in this paper

  • ...In the longchannel case, the subthreshold slope can be improved by increasing the buried oxide (BOX) thickness [2]....

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Journal ArticleDOI
TL;DR: In this article, a method for fabricating a back-gate ground plane underneath a thin-film silicon-on-insulator (SOI) MOSFET is described.
Abstract: A method for fabricating a back-gate ground plane underneath a thin-film silicon-on-insulator (SOI) MOSFET is described. It is shown by numerical simulation that the formation of the ground plane improves the subthreshold slope and short-channel characteristics of very short-channel devices.

36 citations


"Process variation study of Ground P..." refers methods in this paper

  • ...The ground plane (GP) concept is one of the techniques used to reduce the DIBL effect [3]–[5], and it is effective only when the distance between the GP and the drain is small, compared to the channel length [1]....

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