Patent•
Programmable JTAG network architecture to support proprietary debug protocol
30 Oct 1998-
TL;DR: An apparatus capable of testing a plurality of JTAG compliant integrated circuits where at least one of the integrated circuits includes an enhanced embedded debug module is described in this article, where the apparatus is capable of selectively testing certain integrated circuits located at specified locations.
Abstract: An apparatus capable of testing a plurality of JTAG compliant integrated circuits where at least one of the integrated circuits includes an enhanced embedded debug module is described. The apparatus is capable of selectively testing certain of the integrated circuits located at specified locations. In this way, integrated circuits included in a target device having defective or missing integrated circuits can still be tested. The apparatus also allows access to enhanced JTAG debug protocol within a mixed IC (OCDS and non-OCDS) network.
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29 Nov 2000TL;DR: In this paper, techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described, where the hardware designs have been designed in HDL and have been fabricated in integrated circuit products with limited input/output pins.
Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
226 citations
Patent•
28 Nov 2000TL;DR: In this paper, the authors present techniques and systems for debugging an electronic system having instrumentation circuitry included therein, which facilitate analysis, diagnosis and debugging fabricated hardware designs at a HDL level.
Abstract: Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
99 citations
Patent•
02 Mar 2001Abstract: The invention relates to a software system and method for dynamically varying context sensitive menus of a software system. In this method, a menu item is added to a context sensitive menu of a graphical user interface (GUI) at the request of a subsystem module. Then, an activation event for the context sensitive menu is received from the GUI. The added menu item is displayed as either active or inactive based on a response to a query from the software system to a second subsystem module. The action associated with the menu item specified by the first subsystem module is executed when the menu item is selected only if it is active.
91 citations
Patent•
06 Jun 2003
TL;DR: In this article, techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at the hardware description language (HDL) level are described, although the hardware designs were designed in HDL and have been fabricated in integrated circuit products with limited input/output pins.
Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs
69 citations
Patent•
13 Apr 2007TL;DR: In this paper, techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described, which enable the hardware designs within the integrated circuit products to be analyzed and diagnosed at the HDL level at speed.
Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs. Moreover, various embodiments related to HDL code coverage are described.
56 citations
References
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Patent•
IBM1
TL;DR: In this article, a service interface includes a plurality of core interface units integrated with selected cores on the device and coupled to the service access port through a master interface unit that is configured to request at least one of the core interfaces to initiate execution of a predetermined service operation.
Abstract: A data processing system, integrated circuit device, program product, and method thereof utilize a service interface to provide external access to a plurality of cores integrated into an integrated circuit device. The service interface, which may be utilized to perform external data transfer through a service access port in connection with a predetermined service operation, is separate from any function interface that is utilized during regular operation of the device. The service interface includes a plurality of core interface units integrated with selected cores on the device and coupled to the service access port through a master interface unit that is configured to request at least one of the core interface units to initiate execution of a predetermined service operation. As such, a multitude of service operations may be initiated in any number of the cores through a common service access port without occupying a large number of I/O pins and without necessitating interruption of the regular operation of the device.
168 citations
Patent•
02 Jun 1987TL;DR: In this article, a modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry.
Abstract: A modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry. Each of the modules has a test port, which is independent from the system bus interconnections in the logic circuit, and which has an SRL for receiving serial data for selection of the scan path within the module. Responsive to the logic state stored in a module's selection SRL, the scan path within the module will either be enabled or disabled. After selection of a module or modules for testing, serial data is scanned into the SRLs in the scan path for setting the associated predetermined functional circuitry nodes; after exercise of the functional circuitry, the SRLs in the scan path store the results of the exercise at the predetermined nodes. An additional SRL is contained within each test port, and in the scan path, for storing a logic state corresponding to whether the functional circuitry in the module is to be connected to or disconnected from the system bus during the test sequence. A configuration if further disclosed which has global SRLs in the modules; such global SRLs are always in the scan path, regardless of whether or not the module containing them is selected. Multiplexing of the scan data and the configuration data is also disclosed.
100 citations
Patent•
16 Dec 1996TL;DR: In this article, a method of testing an integrated circuit (IC) with multiple modules is presented, which is an extension of IEEE 1149.1 and can be used for hardware and software debugging.
Abstract: A method of testing an integrated circuit 104 which may have multiple modules 204a-d is provided. Target interface 200 provides an interface for connecting target system 104 to a test system which is an extension of IEEE 1149.1. Target system 104 may have multiple devices 202, each having multiple modules 204. Each device 202 has device interface 210 which connects to target interface 200. Decoder 1020 decodes certain signals from interface 200 to enable Extended Operating Modes which allow test codes to be easily directed to any one of modules 204a-d. Hardware and software debugging of system 104 is aided by interface 200 and production testing of system 104 is simplified.
96 citations
Patent•
13 Nov 1995TL;DR: In this article, the boundary-scan registers (18) on the master and slave components (20, 22) are partitioned into external sections (26, 34) and internal sections (28, 36).
Abstract: A JTAG module (12) includes a master component (20) and any number of slave components (22). The master component (20) includes a TAP controller (24) and related control circuits. Through a control bus (35), the TAP controller (24) on the master component (20) controls boundary-scan registers (18) on the slave components (22). The boundary-scan registers (18) in the slave components (22) form a boundary-scan chain that originates and terminates at the master component (20). TAP controller circuitry may be omitted from the slave components (22). The boundary-scan registers (18) on the master and slave components (20, 22) are partitioned into external sections (26, 34) and internal sections (28, 36). The external sections couple to conductive traces (46) which are accessible from outside the module (12). The internal sections couple to conductive traces (48) which are substantially inaccessible from outside the module (12).
88 citations
Patent•
22 Mar 1991TL;DR: In this paper, three shift path circuits (10, 20, 30') each comprising a bypass circuit are connected in series between a test data input (TDI) and test data output (TDO), each shift path circuit constitutes a design definition test data register connected to a circuit to be tested.
Abstract: Three shift path circuits (10', 20', 30') each comprising a bypass circuit are connected in series between a test data input (TDI) and a test data output (TDO). Each shift path circuit constitutes a design definition test data register connected to a circuit to be tested. Design modification of a testing circuit can be minimized by selectively operating the bypass circuit provided in a shift path circuit, even if there is circuit modification in the circuit to be tested. The period of time required for testing circuits to be tested is reduced.
69 citations