Progress and challenges in VLSI placement research
05 Nov 2012-pp 275-282
TL;DR: The history of placement research, the progress leading up to the state of the art, and outstanding challenges are surveyed.
Abstract: Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.
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TL;DR: This work experimentally validates a promising path towards practical beyond-silicon electronic systems and proposes a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates.
Abstract: Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal–oxide–semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems. A 16-bit microprocessor built from over 14,000 carbon nanotube transistors may enable energy efficiency advances in electronics technologies beyond silicon.
423 citations
TL;DR: Fundamental limits to computation in the areas of manufacturing, energy, physical space, design and verification effort, and algorithms are reviewed, to outline what is achievable in principle and in practice.
Abstract: To evaluate the promise of potential computing technologies, this review examines a wide range of fundamental limits, such as to performance, power consumption, size and cost, from the device level to the system level. Computers have evolved at a remarkable rate, with improvements over the past fifty years roughly in line with Gordon Moore's prescient observation that the number of transistors in a dense integrated circuit would double approximately every two years. The rate of 'Moore scaling' is slowing down and other physical limits are looming, but new technologies such as carbon nanotubes, graphene and quantum computation are on the way. In this Review, Igor Markov takes a fresh look at the fundamental limits at various levels, from devices to complete systems, and compares loose and tight limits. Markov argues that the study of the limits of fundamental limits to computation can lead to new insights for emerging technologies. An indispensable part of our personal and working lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the past fifty years. Such Moore scaling now requires ever-increasing efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and increase our understanding of integrated-circuit scaling, here I review fundamental limits to computation in the areas of manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, I recapitulate how some limits were circumvented, and compare loose and tight limits. Engineering difficulties encountered by emerging technologies may indicate yet unknown limits.
366 citations
Cites background from "Progress and challenges in VLSI pla..."
...In 2010, physical separation of modules became less critical, as large-scale placement optimizations assumed greater responsibility for IC layout and learned to blend nearby modules [33, 34]....
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01 Jan 2016
TL;DR: This living document is pleased to provide this living document for unlocking the evergrowing vocabulary of abbreviations and acronyms of the telecommunications world.
Abstract: physical design electronics wikipedia in integrated circuit design physical design is a step in the standard design cycle which follows after the circuit design at this step circuit representations of, integrated circuit layout wikipedia integrated circuit layout also known ic layout ic mask layout or mask design is the representation of an integrated circuit in terms of planar geometric shapes, engineering courses concordia university concordia university http www concordia ca content concordia en academics graduate calendar current encs engineering courses html, peer reviewed journal ijera com international journal of engineering research and applications ijera is an open access online peer reviewed international journal that publishes research, telecommunications abbreviations and acronyms consultation erkan is pleased to provide this living document for unlocking the evergrowing vocabulary of abbreviations and acronyms of the telecommunications world, contents international information institute vol 7 no 3 may 2004 mathematical and natural sciences study on bilinear scheme and application to three dimensional convective equation itaru hataue and yosuke
183 citations
TL;DR: In this article, the authors presented a deep reinforcement learning approach to chip floorplanning, which can automatically generate chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area.
Abstract: Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields. Machine learning tools are used to greatly accelerate chip layout design, by posing chip floorplanning as a reinforcement learning problem and using neural networks to generate high-performance chip layouts.
124 citations
References
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01 Jan 1982
TL;DR: An iterative mincut heuristic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network.
Abstract: An iterative mincut heuristic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network. In practice, only a very small number of passes are typically needed, leading to a fast approximation algorithm for mincut partitioning. To deal with cells of various sizes, the algorithm progresses by moving one cell at a time between the blocks of the partition while maintaining a desired balance based on the size of the blocks rather than the number of cells per block. Efficient data structures are used to avoid unnecessary searching for the best cell to move and to minimize unnecessary updating of cells affected by each move.
2,463 citations
"Progress and challenges in VLSI pla..." refers methods in this paper
...Despite the steady improvement of analytical placement, partitioning-based methods improved enough to provide leading-edge performance: 1) (multilevel) Fiduccia–Mattheyses (FM) [63] heuristics produced much better results much faster than previous methods; 2) the use of end-case techniques (optimal partitioning and end-case placement) during top– down layout optimization provided high-quality detailed placement [18]; and 3) the use of flat and multilevel FM heuristics was carefully optimized, including cutline selection and hierarchical whitespace allocation [24]....
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Book•
10 Dec 1996
TL;DR: PDE examples by type linear problems as mentioned in this paper, including nonlinear stationary problems, nonlinear evolution problems, and nonlinear Cauchy problems, can be found in this paper.
Abstract: PDE examples by type Linear problems...An introduction Nonlinear stationary problems Nonlinear evolution problems Accretive operators and nonlinear Cauchy problems Appendix Bibliography Index.
1,379 citations
01 Sep 1997
TL;DR: In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
Abstract: We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today's industrial designs.
1,133 citations
Book•
31 Jan 1993
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.
Abstract: From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.
927 citations