AIP Advances 6, 125119 (2016); https://doi.org/10.1063/1.4973429 6, 125119
© 2016 Author(s).
Prolonged silicon carbide integrated circuit
operation in Venus surface atmospheric
conditions
Cite as: AIP Advances 6, 125119 (2016); https://doi.org/10.1063/1.4973429
Submitted: 23 September 2016 • Accepted: 16 December 2016 • Published Online: 27 December 2016
Philip G. Neudeck, Roger D. Meredith, Liangyu Chen, et al.
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AIP ADVANCES 6, 125119 (2016)
Prolonged silicon carbide integrated circuit operation
in Venus surface atmospheric conditions
Philip G. Neudeck,
1,
a
Roger D. Meredith,
1
Liangyu Chen,
2
David J. Spry,
1
Leah M. Nakley,
1
and Gary W. Hunter
1
1
NASA Glenn Research Center, 21000 Brookpark Road, M.S. 77-1, Cleveland,
Ohio 44135, USA
2
OAI/NASA Glenn, 21000 Brookpark Road, M.S. 77-1, Cleveland, Ohio 44135, USA
(Received 23 September 2016; accepted 16 December 2016; published online
27 December 2016)
The prolonged operation of semiconductor integrated circuits (ICs) needed for
long-duration exploration of the surface of Venus has proven insurmountably chal-
lenging to date due to the ∼ 460
◦
C, ∼ 9.4 MPa caustic environment. Past and
planned Venus landers have been limited to a few hours of surface operation, even
when IC electronics needed for basic lander operation are protected with heavily
cumbersome pressure vessels and cooling measures. Here we demonstrate vastly
longer (weeks) electrical operation of two silicon carbide (4H-SiC) junction field
effect transistor (JFET) ring oscillator ICs tested with chips directly exposed (no
cooling and no protective chip packaging) to a high-fidelity physical and chemi-
cal reproduction of Venus’ surface atmosphere. This represents more than 100-fold
extension of demonstrated Venus environment electronics durability. With further
technology maturation, such SiC IC electronics could drastically improve Venus lan-
der designs and mission concepts, fundamentally enabling long-duration enhanced
missions to the surface of Venus. © 2016 Author(s). All article content, except where
otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license
(
http://creativecommons.org/licenses/by/4.0/). [http://dx.doi.org/10.1063/1.4973429]
Authoritative expert panel reports have described why improved understanding of Venus and
its greenhouse effect atmosphere and geology has relevance to a better understanding of the Earth
and solar system formation.
1–4
Towards this end, these reports call for surface observations that will
require prolonged-mission Venus landers, including long-term atmospheric and seismic activity data.
While long-term operation of silicon-based ICs has enabled years of useful Mars lander mission
duration,
1,5,6
achieving similar mission duration on the surface of Venus has proven an insurmountable
challenge to date.
5–8
Venus’ thick CO
2
-based atmosphere supports massive greenhouse warming
and extreme physical conditions (∼460
◦
C, ∼ 94 MPa, above CO
2
’s critical point).
7,9
Adding to
the challenge is a caustic atmospheric chemistry containing enough SO
2
(around ∼180 ppm at the
surface) to form sulfuric acid cloud-decks many tens of kilometers thick.
9
As these conditions fall
well beyond the operating realm of silicon-based ICs,
10,11
prior Venus landers and modern designs
for future landers have employed pressure vessels and/or cooling systems to protect mission-critical
IC electronics. These protection measures add substantial mass and mission expense, and are only
effective for a few hours (2 hours, 7 minutes is the surface operation record set by Venera 13) before
the surrounding Venus environment overcomes the protection and thermally fails the electronics with
silicon ICs bringing end of mission.
3,5–8
Other groups have reported short term (i.e., far less than 500 hours) T ≥ 460
◦
C Earth-atmosphere
operation of SiC and III-N integrated circuits with single-level interconnect.
12–23
Recently our group
at NASA Glenn reported the fabrication and demonstration of 4H-SiC JFET integrated circuits (up
to 24 transistors, with two levels of metal interconnect) and ceramic packaging that have consistently
a
Author to whom correspondence should be addressed. Electronic mail:
Neudeck@nasa.gov.
2158-3226/2016/6(12)/125119/7 6, 125119-1 © Author(s) 2016
125119-2 Neudeck et al. AIP Advances 6, 125119 (2016)
functioned for more than 1000 hours (41.7 days) at 500
◦
C in Earth-atmosphere oven-testing.
24–26
Given these promising results, we decided to subject other chips diced from the same prototype IC
wafer to electrical testing in simulated Venus surface atmospheric conditions inside the NASA Glenn
Extreme Environments Rig (GEER).
27
Ring oscillator chips were selected for the first such test, as
these ICs can be operated using the fewest number of wires (one signal output in addition to +V
DD
,
GND, and -V
SS
chip DC power inputs), are a recognized standard for logic IC demonstration, and
provide harmonic output signals that can be detected in frequency spectrum even in the presence of
substantial expected electrical noise and output signal path attenuation. Two NASA Glenn fabricated
SiC JFET ring oscillator ICs residing on separate chips were selected for testing in GEER: a 3-stage
ring oscillator and an 11-stage ring oscillator that are further described in the supplementary material
and elsewhere.
24–26,28
Two electrical feedthrough probe assemblies that are further described in the supplementary
material
were custom-built to enable operational testing of these chips exposed to simulated Venus
surface atmosphere in GEER. Each probe assembly nominally provided four outside-chamber elec-
trical connections to the SiC IC chip inside the chamber. The limited number of available test ports on
FIG. 1. Annotated photographs documenting the chip-containing end of the 11-stage ring oscillator feedthrough probe assem-
bly at various stages of this study. (a) Nearly-completed assembly showing the 3 mm x 3 mm 11-stage SiC ring oscillator
chip attached to ceramic substrate and fiberglass-sleeved wiring bundle prior to any heated testing. (b) Completed assembly
prior to heated testing showing the mesh screen cap that permits chip immersion in simulated Venus atmosphere during the
test. (c) After 21.7 days of simulated Venus surface conditions testing following removal of the mesh screen cap. (d) During
clip-lead electrical testing conducted with the chip disconnected/isolated from the short-circuited feedthrough by removal of
the nickel alloy wires.
125119-3 Neudeck et al. AIP Advances 6, 125119 (2016)
the GEER chamber, limited space and number wires in the first custom feedthrough probe design, and
lengthy processes of probe construction, pressure qualification, and safety approval were all factors
that combined to restrict the sample size for this first feasibility test to just two SiC ICs. Figure
1 shows
the inside-chamber end of one such probe assembly at various stages of the experiment. Fig.
1(a)
shows the mounting and wiring of the 3 mm x 3 mm 11-stage SiC JFET ring oscillator IC chip
almost ready for testing. Electrical signals were routed through mineral insulated cable comprised
of four Nickel 201 (alloy) wires separated by crushed magnesium oxide ceramic insulation material
inside an Inconel 600 jacket, sealed at both ends by multiple cycles of manually applying and curing
Ferro 1180A high temperature glass. The subsequently installed cover with wire-mesh screen seen in
Fig.
1(b) permitted simulated Venus atmosphere immersion of the chip, wire bonds, die attach, and
ceramic substrate during the test, whilst protecting these from physical damage during feedthrough
probe handling and mounting. Prior to simulated Venus surface conditions testing, both feedthrough
probes with chips were operationally qualified 1) in Earth-atmosphere 460
◦
C to 480
◦
C tube oven
for over 47 hours, and 2) installed in GEER under nitrogen atmosphere of 460
◦
C and 9.0 MPa for
56 hours.
Two 4-conductor cables (more than 14 m long) routed through safety wall bulkheads electri-
cally connected each chip/probe assembly to computer-controlled instruments. As discussed in the
supplementary material, the setup greatly attenuates measured oscillator IC output signals to varying
degree that depends upon a number of experimental factors, including oscilloscope probe loading,
cable parasitics and length, IC output signal frequency and impedance, and electrical parasitics of the
custom-built feedthroughs. However, since the IC output buffers largely isolate the critical feedback
ring circuit loop, oscillator output frequencies are much less affected by these varying off-chip signal
path conduction factors. A dual-output supply provided V
DD
= +24 V and V
SS
=
☞
24 V DC power
to both chips for all the testing in GEER. Two computer-controlled relays, each residing between
FIG. 2. SiC ring oscillator IC testing data summary as a function of time in Venus surface atmospheric conditions. (a) Recorded
GEER vessel temperature (red, solid) and pressure (blue, dashed). (b) Measured SiC ring oscillator IC output signal frequencies.
The 3-stage SiC JFET ring oscillator IC (top trace, purple) functioned at 1.26 ± 0.05 MHz over the entire 521 hours (21.7 days)
it was exposed to Venus surface atmospheric conditions. The 11-stage ring oscillator IC (bottom trace, green) functioned at
245 ± 5 kHz for 109 hours, after which output signal degraded and was lost at 161 hours; however, as shown in Fig.
4(b),
this IC was later verified fully functional following post-test disconnection from its electrical feedthrough that short-circuited
during Venus conditions testing. Data from some of the pre-test heat-up and post-test cool-down is also shown.
125119-4 Neudeck et al. AIP Advances 6, 125119 (2016)
respective feedthrough probe V
DD
cable wire inputs and the V
DD
power supply output terminal,
were inserted to facilitate independent powering and measurement of each oscillator as well as mea-
surement of “power-off” background noise waveforms. More information on the GEER vessel and
experimental procedures is in the supplementary material.
Figure
2 summarizes the experimental test results as a function of time in simulated Venus surface
atmospheric conditions. Figure
2(a) shows the measured GEER chamber pressure and temperature.
The reference time t = 0 hours corresponds to GEER arriving at 460
◦
C and 9.4 MPa pressure with the
simulated Venus surface atmospheric composition. 521 hours (21.7 days) of simulated Venus surface
conditions testing time were accumulated before facility scheduling forced test conclusion. Measure-
ments for some of the pre-testing ramp-up and post-testing cool-down are included in Fig.
2 plots,
showing expected oscillation frequency dependence on temperature.
29
The oscillation frequency ratio
between the two ICs differs somewhat from the 11 to 3 ratio that would be expected based solely
on number of signal feedback loop gates/stages, but further study is required to firmly ascertain the
reasons behind this discrepancy.
Figure
2(b) shows the measured oscillation frequencies of the two ICs throughout the Venus
conditions testing. As seen in Fig.
2(b) and Fig. 3, the 3-stage ring oscillator IC functioned at
1.26 ± 0.06 MHz for the entire 521 hour (21.7 days) duration in simulated Venus surface condi-
tions. This time of IC operation in Venus surface atmospheric conditions is more than 100-fold
longer than what has been previously demonstrated 1) without a protective enclosure or cooling and
2) on actual Venus landers with heavily cumbersome electronics-protection measures.
5,7
“Power off”
control waveforms recorded throughout the testing confirmed that no oscillation signal was present
FIG. 3. Three-stage ring oscillator IC output signal recorded at 521 hours of simulated Venus surface conditions operation.
(a) 10 µsec window of waveform data measured with 3-stage oscillator V
DD
powered (V
DD
relay closed, solid red) and
unpowered (V
DD
relay open, dashed blue). (b) Fast Fourier Transform (FFT) magnitude spectra calculated from full recorded
waveforms, illustrating that fundamental (1.21 MHz) and third-order harmonic (3.63 MHz) FFT peaks are present only when
the 3-stage SiC ring oscillator is properly powered with the V
DD
relay closed (solid red) and not present when the V
DD
relay
is open (dashed blue). The IC output signal amplitude is substantially attenuated by feedthrough and cabling between the
chip and the measurement oscilloscope, but the amount of attenuation could not be independently quantified during the Venus
conditions testing.