Propagation Delay-Based Expression of Power Supply-Induced Jitter Sensitivity for CMOS Buffer Chain
TL;DR: This paper demonstrates a very simple and highly accurate expression of power supply-induced jitter sensitivity transfer function for CMOS buffer chain.
Abstract: This paper demonstrates a very simple and highly accurate expression of power supply-induced jitter sensitivity transfer function for CMOS buffer chain. The transfer function is mainly a function of the maximum and minimum propagation delay of the buffer chain. The function can be easily obtained and used in jitter budget calculation.
Citations
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TL;DR: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ).
Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.
45 citations
Cites background or methods from "Propagation Delay-Based Expression ..."
...Since the total delay is a function of propagation delays of each of the small sections, the propagation delay can be expressed as [41], [43]...
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...Reference [41] concludes that jitter depends on the propagation delay....
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...Reference [41] discusses the power supply jitter sensitivity calculation despite knowing the architecture of the buffer chain and its electrical parameters....
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...1) Jitter Sensitivity Based on Propagation Delay: A method for the calculation of PSIJ sensitivity function based on the propagation delay is discussed in [41] and is explained by a flowchart in Fig....
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...The total delay of the buffer chain is given in [41]...
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TL;DR: An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.
Abstract: This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.
30 citations
Cites background from "Propagation Delay-Based Expression ..."
...In [20] and [21], the same is analyzed for a chain of inverters where the transfer function from power supply to the output jitter of N -cascaded inverter stages is derived....
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TL;DR: In this paper, an efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented, based on separating the large signal response and the small signal noise response and subsequently combining the results.
Abstract: An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources.
30 citations
Cites methods from "Propagation Delay-Based Expression ..."
...Wang and Kwasniewski [18] propose an RC delay-based technique to estimate PSIJ sensitivity of a CMOS buffer chain....
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...The other analytical methods deal mostly with single-ended buffer or a chain of buffers [13]–[18]....
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TL;DR: The full PSIJ transfer function model is significantly simplified, which provides physical insights of PSIJ at inverter chains and is successfully validated by SPICE simulations with 130 nm CMOS technology.
Abstract: Precise analytical models of power supply noise induced jitter (PSIJ) at inverter chains are proposed. Based on the piecewise linear approximated I–V curve model, analytical models of local PSIJ transfer functions at local rising and falling edges are derived. The total PSIJ transfer function of an inverter chain output is then estimated by alternately accumulating the local PSIJ transfer function at local rising and falling edges. Based on several assumptions, the full PSIJ transfer function model is significantly simplified, which provides physical insights of PSIJ at inverter chains. Accuracy of the proposed analytical model is successfully validated by SPICE simulations with 130 nm CMOS technology. In addition, properties of the PSIJ transfer function at inverter chains are analyzed based on the proposed model.
27 citations
Cites background from "Propagation Delay-Based Expression ..."
...Technol., vol. 3, no. 1, pp. 113–125, Jan. 2013.. [11] X. J. Wang and T. Kwasniewski, “Propagation delay-based expression of power supply-induced jitter sensitivity for CMOS buffer chain,” IEEE Trans....
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...Wang and Kwasniewski [11] proposed a simple expression of PSIJ sensitivity at the inverter chain based on RC delay models....
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TL;DR: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented and a significant speedup is demonstrated using the proposed approach.
Abstract: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach.
13 citations
Cites methods from "Propagation Delay-Based Expression ..."
...A delay-based technique for a chain of buffers, which also requires IFFT computation, can be found in [24] and via analytical techniques in [25] and [26]....
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References
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TL;DR: This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency, and shows that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling.
Abstract: This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show through extensive analysis techniques that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on 130- and 180-nm processors validate the approach.
110 citations
01 Jun 2003
TL;DR: An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics, consistent with short-channel MOSFET behavior, including carrier velocity saturation effects.
Abstract: Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.
71 citations
"Propagation Delay-Based Expression ..." refers background in this paper
...At the same time, scaling of power supply levels and improving transconductance of devices have increased the sensitivity of buffers to power supply-induced delays [2]....
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TL;DR: The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer from a linear differential equation obtained from asymptotic linear inverter I-V curves.
Abstract: The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer. The analytic transfer functions are derived from a linear differential equation obtained from asymptotic linear inverter I-V curves. The transfer functions are validated by comparison with HSPICE simulations. The estimated jitter is compared with the simulated jitter using eye diagrams with single-frequency and multitone supply voltage fluctuations.
44 citations
"Propagation Delay-Based Expression ..." refers background in this paper
...In [3] and [4], PSIJS of a single inverter is provided but not for buffer chain with the inverters of different sizes....
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21 Nov 2007
TL;DR: In this article, a detailed analysis of supply noise induced jitter in a high-speed interface is presented, where the sensitivity of the interface circuits to noise is measured as a function of noise frequency.
Abstract: Minimizing the jitter due to supply noise is the most important design goal for the power delivery system of highspeed interfaces. We present a detailed analysis of supply noise induced jitter in a high-speed interface. We first simulate the supply noise spectrum generated in the interface. We then measure the sensitivity of the interface circuits to noise as a function of noise frequency. Next, we analyze the jitter spectrum by combining these two parameters. Based on this analysis, we observe large jitter contributions at medium frequencies. This is not expected if we consider only the supply noise current spectrum since the medium frequency is way below the data rate or the frequencies of internal clock signals. However, it can be easily explained with the power supply network impedance profile. Finally, we correlate the predicted jitter spectrum with the measured jitter spectrum of a serial link operating at 6.4 Gbps.
44 citations
"Propagation Delay-Based Expression ..." refers background in this paper
...Jitter sensitivity is defined as the ratio between the jitter generated by a single-frequency supply noise signal divided by the amplitude of this noise signal [9]....
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10 Oct 2011
TL;DR: The transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions and validated by comparison with HSPICE simulation.
Abstract: In this paper, the transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions. The expressions for the jitter transfer function is validated by comparison with HSPICE simulation, and applied to an example for statistical jitter estimation.
31 citations
"Propagation Delay-Based Expression ..." refers background in this paper
...In [3] and [4], PSIJS of a single inverter is provided but not for buffer chain with the inverters of different sizes....
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