Proposed high speed packet switch for broadband integrated networks
TL;DR: The design of a high speed, broadband packet switch with two priority levels for application in integrated voice/data networks is presented and the design is implemented by task-sharing in a multi-processor configuration.
About: This article is published in Computer Communications.The article was published on 1989-12-01. It has received 9 citations till now. The article focuses on the topics: Burst switching & Transmission delay.
Citations
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TL;DR: This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.
Abstract: The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.
108Â citations
Patent•
06 Jul 1998
TL;DR: In this paper, a group switching center for data communications and teleprocessing is provided, which comprises first routing switches having a plurality of sending ports ( 51, 53, 55, 57, 56, 57 ) and a plurality receiving ports ( 50, 52, 54, 56, 56 ), each sending port adapted to be operatively connected to a receiving data terminal equipment unit (10, 28, 29 ) or to a sending port of second routing switch ( 32, 34 ), each receiving port adapted with a sending data terminal unit ( 10, 28 and 29 ), and each receiving ports
Abstract: A videoconferencing center ( 31, 33 ) for data communications and teleprocessing is provided which comprises first routing switches having a plurality of sending ports ( 51, 53, 55, 57 ) and a plurality of receiving ports ( 50, 52, 54, 56 ), each sending port adapted to be operatively connected to a receiving data terminal equipment unit ( 10, 28, 29 ) or to a receiving port of second routing switch ( 32, 34 ), each receiving port adapted to be operatively connected to a sending data terminal equipment unit ( 10, 28, 29 ) or to a sending port of another group switching center ( 32, 34 ). Each receiving port is assigned a receiving stack ( 102 ) that is addressable in a single logical address space and each sending port is assigned a sending stack ( 103 ) for containing addresses of said single logical address space. The single logical address reduces the risk of losing data received, which risk results from the necessary limits on physical addresses of stacks. This group switching center is particularly useful for high-speed links of the type that may be required for a videoconferencing system.
10Â citations
TL;DR: A novel design of a high speed packet switch capable of catering to voice and data traffic is described and the performance of the network and the packet switch is evaluated for various traffic characteristics through a simulation.
Abstract: This paper proposes a packet switched broadband integrated network, for multi-rate services such as voice and data. A novel design of a high speed packet switch capable of catering to voice and data traffic is described. Some sources of traffic bottle-necks are identified, and methods of clearing the bottle-necks through flow control techniques are discussed. The design and flow control parameters are obtained through simulation, and the results are presented. The performance of the network and the packet switch is evaluated for various traffic characteristics through a second simulation, and the results are briefly presented.
8Â citations
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...The "Post Office" packet switch [8] depicted in Fig....
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28 Nov 1994
TL;DR: A scalable two-stage switching hub platform is proposed for private network environment with ATM-ready capabilities and an implementation-leading approach of the MIA, a generalized multisubsystem interconnect adapter, is presented.
Abstract: Internetworking of FDDI, Ethernet or other local area networks including the ATM-LAN to the public ATM networks will involve the development of the ATM hub. Taking the performance and cost-effective factors into account, a scalable two-stage switching hub platform is proposed for private network environment with ATM-ready capabilities. Packet as well as cell switching architectures are adopted for the design of the switching fabrics. The architecture applies the concept of each source/destination port pair with dedicated input and output queues. A generalized multisubsystem interconnect adapter (MIA) is also proposed for heterogeneous subsystems to a common switching fabric. The design complexity versus performance of the I/O queues' number and length are analyzed. Finally, an implementation-leading approach of the MIA is presented.
5Â citations
02 Oct 1994
TL;DR: A two-stage switching hub for LAN interconnection is designed and presented and has been proved to have the advantages of very low latency, flexible scalability and easy routing management with two-way learning.
Abstract: As broadband multimedia applications to the desk top are becoming popular today, the high-speed bandwidth demand from a single user will occupy large shares of the LAN's channel capacity. Therefore, the evolution of LAN technologies has shifted from shared to dedicated media. More and more LANs are being installed and their interconnection will require parallel switching techniques such as a high-speed switching hub. The ATM small cell-size switching approach is intended to accommodate the mixed media such as voice, data and video. To fulfil the switching cost, bandwidth and latency criteria, a two-stage switching hub for LAN interconnection is designed and presented in this paper. The packet switching technique is used in the first stage switching to efficiently interconnect the local LANs. For the second stage design, the ATM cell switching is adopted to accommodate multimedia traffic and internetworking among LANs and WANs. The switching architecture including both the packet and cell switching units is thoroughly described. The message flow and routing mechanism are presented in the paper. This architecture has been proved to have the advantages of very low latency, flexible scalability and easy routing management with two-way learning. >
3Â citations
References
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Book•
02 Jan 1991
TL;DR: A new, high-performance packet-switching architecture, called the Knockout Switch, is proposed, which uses a novel concentrator design at each output to reduce the number of separate buffers needed to receive simultaneously arriving packets.
Abstract: A new, high-performance packet-switching architecture, called the Knockout Switch, is proposed. The Knockout Switch uses a fully interconnected switch fabric topology (i.e., each input has a direct path to every output) so that no switch blocking occurs where packets destined for one output interfere with (i.e., block or delay) packets going to different Outputs. It is only at each output of the switch that one encounters the unavoidable congestion caused by multiple packets simultaneously arriving on different inputs all destined for the same output. Taking advantage of the inevitability of lost packets in a packet-switching network, the Knockout Switch uses a novel concentrator design at each output to reduce the number of separate buffers needed to receive simultaneously arriving packets. Following the concentrator, a shared buffer architecture provides complete sharing of all buffer memory at each output and ensures that all packets are placed on the output line on a first-in first-out basis. The Knockout Switch architecture has low latency, and is self-routing and nonblocking. Moreover, its Simple interconnection topology allows for easy modular growth along with minimal disruption and easy repair for any fault. Possible applications include interconnects for multiprocessing systems, high-speed local and metropolitan area networks, and local or toll switches for integrated traffic loads.
629Â citations
TL;DR: The Knockout Switch as discussed by the authors uses a fully interconnected switch fabric topology (i.e., each input has a direct path to every output) so that no switch blocking occurs where packets destined for one output interfere with (block or delay) packets going to different Outputs.
Abstract: A new, high-performance packet-switching architecture, called the Knockout Switch, is proposed. The Knockout Switch uses a fully interconnected switch fabric topology (i.e., each input has a direct path to every output) so that no switch blocking occurs where packets destined for one output interfere with (i.e., block or delay) packets going to different Outputs. It is only at each output of the switch that one encounters the unavoidable congestion caused by multiple packets simultaneously arriving on different inputs all destined for the same output. Taking advantage of the inevitability of lost packets in a packet-switching network, the Knockout Switch uses a novel concentrator design at each output to reduce the number of separate buffers needed to receive simultaneously arriving packets. Following the concentrator, a shared buffer architecture provides complete sharing of all buffer memory at each output and ensures that all packets are placed on the output line on a first-in first-out basis. The Knockout Switch architecture has low latency, and is self-routing and nonblocking. Moreover, its Simple interconnection topology allows for easy modular growth along with minimal disruption and easy repair for any fault. Possible applications include interconnects for multiprocessing systems, high-speed local and metropolitan area networks, and local or toll switches for integrated traffic loads.
589Â citations
TL;DR: A broadband (total throughput approaching 1 terabit/s) self-routing packet switch design for providing flexible multiple bit-rate broadband services for an end-to-end fiber network is given and the throughput per port is improved by means of parallel switch fabric, while maintaining the periodic nature of the traffic.
Abstract: This paper gives a broadband (total throughput approaching 1 terabit/s) self-routing packet switch design for providing flexible multiple bit-rate broadband services for an end-to-end fiber network. The switch fabric for the slotted broadband packet switch delivers exactly one packet to each output port from one of the input ports which request packet delivery to that output port. The denied requests would try again during the next slot. We discover an effective scheme, implemented by CMOS VLSI with manageable complexity, for performing this function. First, each input port sends a request for a port destination through a Batcher Sorting network, which sorts the request destinations in ascending order so that we may easily purge all but one request for the same destination. The winning request acknowledges its originating port from the output of the Batcher network, with the acknowledgment routed through a Batcher-banyan selfrouting switch. The acknowledged input port then sends the full packet through the same Batcher-banyan switch without any conflict. Unacknowledged ports buffer the blocked packet for reentry in the next cycle. We also give several variations for significantly improved performance. We then study switch performance based on some rudimentary protocols for traffic control. For the basic scheme, we analyze the throughput-delay characteristics for random traffic, modeled by random output port requests and a binomial distribution of packet arrival. We demonstrate with a buffer size of around 20 packets, we can achieve a 50 percent loading with almost no buffer overflow. Maximum throughput of switch is 58 percent. Next, we investigate the performance of the switch in the presence of periodic broadband traffic. We then apply circuit switching techniques and packet priority for high bit-rate services in our packet switch environment. We improve the throughput per port to close to 100 percent by means of parallel switch fabric, while maintaining the periodic nature of the traffic.
510Â citations
TL;DR: Large-scale packet speech multiplexing experiments could not be carried out on ARPANET or SATNET where the network link capacities severely restrict the number of speech users that can be accommodated, but experiments are currently being carried out using a wide-band satellite-based packet system designed to accommodate a sufficient number of simultaneous users to support realistic experiments in efficient statisticalmultiplexing.
Abstract: The integration of digital voice with data in a common packet-switched network system offers a number of potential benefits, including reduced systems cost through sharing of switching and transmission resources, flexible internetworking among systems utilizing different transmission media, and enhanced services for users requiring access to both voice and data communications. Issues which it has been necessary to address in order to realize these benefits include reconstitution of speech from packets arriving at nonuniform intervals, maximization of packet speech multiplexing efficiency, and determination of the implementation requirements for terminals and switching in a large-scale packet voice/data system. A series of packet speech systems experiments to address these issues has been conducted under the sponsorship of the Defense Advanced Research Projects Agency (DARPA). In the initial experiments on the ARPANET, the basic feasibility of speech communication on a store-and-forward packet network was demonstrated. Techniques were developed for reconstitution of speech from packets, and protocols were developed for call setup and for speech transport. Later speech experiments utilizing the Atlantic packet satellite network (SATNET) led to the development of techniques for efficient voice conferencing in a broadcast environment, and for internetting speech between a store-and-forward net (ARPANEI) and a broadcast net (SATNET). Large-scale packet speech multiplexing experiments could not be carried out on ARPANET or SATNET where the network link capacities severely restrict the number of speech users that can be accommodated. However, experiments are currently being carried out using a wide-band satellite-based packet system designed to accommodate a sufficient number of simultaneous users to support realistic experiments in efficient statistical multiplexing. Key developments to date associated with the wide-band experiments have been 1) techniques for internetting via voice/data gateways from a variety of local access networks (packet cable, packet radio, and circuit-switched) to a long-haul broadcast satellite network and 2) compact implementations of packet voice terminals with full protocol and voice capabilities. Basic concepts and issues associated with packet speech systems are described. Requirements and techniques for speech processing, voice protocols, packetization and reconstitution, conferencing, and multiplexing are discussed in the context of a generic packet speech system configuration. Specific experimental configurations and key packet speech results on the ARPANET, SATNET, and wide-band system are reviewed.
155Â citations
TL;DR: The most important technology-the bus matrix switch-provides a quantum leap in processing capacity up to several Gbit/s (few millions of packets every second), while keeping a very low switching delay, which will greatly improve for computer networks and will also enable basic and broadband ISDN.
Abstract: For several years, Fujitsu has been researching and developing high-speed packet switching networks, the result being an integrated multimedia information networks architecture. This architecture has already been applied to LAN systems and can now be applied to wide area corporate networks thanks to the new developments described in this paper. The most important technology-the bus matrix switch-provides a quantum leap in processing capacity up to several Gbit/s (few millions of packets every second), while keeping a very low switching delay. The performance evaluation based on our prototype models is also considered in detail. For example, a voice delay of less than 20 ms is obtained for five-hop communication. The new technologies will greatly improve for computer networks and will also enable basic and broadband ISDN.
128Â citations