IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 1, JANUARY 2003 301
Quantization Resolution and Limit Cycling in
Digitally Controlled PWM Converters
Angel V. Peterchev, Student Member, IEEE, and Seth R. Sanders, Member, IEEE
Abstract—This paper discusses the presence of steady-state
limit cycles in digitally controlled pulse-width modulation (PWM)
converters, and suggests conditions on the control law and the
quantization resolution for their elimination. It then introduces
single-phase and multi-phase controlled digital dither as a means
of increasing the effective resolution of digital PWM (DPWM)
modules, allowing for the use of low resolution DPWM units in
high regulation accuracy applications. Bounds on the number
of bits of dither that can be used in a particular converter are
derived. Finally, experimental results confirming the theoretical
analysis are presented.
Index Terms—Analog-digital conversion, digital control, dither,
finite wordlength effects, power conversion, pulse-width modula-
tion, quantization, stability, voltage regulation.
I. INTRODUCTION
D
IGITAL controllers for pulse-width modulation (PWM)
converters enjoy growing popularity due to their low
power, immunity to analog component variations, compatibility
with digital systems, and faster design process, as discussed
in [1] and the references therein. They have the potential to
implement sophisticated control schemes and to accurately
match duty cycles in interleaved converters. Their applications
include microprocessor voltage regulation modules (VRMs),
portable electronic devices, and audio amplifiers, among many
others.
This paper discusses conditions for the elimination of limit
cycles, steady state oscillations at frequencies lower than the
switching frequency, in digitally controlled PWM converters, as
well as techniques for increasing the effective resolution of dig-
ital PWM (DPWM) modules. Section II gives an overview of
the structure of digital PWM controllers. Section III describes
limit cycles and presents conditions for their elimination. Sec-
tion IV introduces controlled digital dither as a technique that
effectively increases the resolution of the DPWM module, al-
lowing for the use of low resolution DPWM modules in applica-
tions requiring high regulation accuracy, such as VRMs. The use
of lowresolution DPWM modules in these applications, without
incurring limit cycles, can result in substantial powerand silicon
area savings. Section V presents results from a prototype con-
verter implementing the findings of this paper.
Manuscript received January 30, 2002; revised December 1, 2002. This work
was presented in part at the Power Electronics Specialists Conference (PESC),
Vancouver, BC, Canada, June 17–22, 2001. Recommended by Associate Editor
S. B. Leeb.
The authors are with the Department of Electrical Engineering and Com-
puter Science, University of California, Berkeley, CA 94720 USA (e-mail: pe-
terch@eecs.berkeley.edu; sanders@eecs.berkeley.edu).
Digital Object Identifier 10.1109/TPEL.2002.807092
II. DIGITAL CONTROLLER STRUCTURE
A block diagram of a digitally controlled PWM buck con-
verter is shown in Fig. 1. The controller consists of an analog-to-
digital converter (ADC) which digitizes the regulated quantity
(e.g., the output voltage
), a DPWM module, and a dis-
crete-time control law. A discrete-time PID control law has the
form
(1)
where
is the duty cycle command at discrete time ,
is the error signal
(2)
and
is the state of an integrator
(3)
Further,
is the proportional gain, is the derivative gain,
and
is the integral gain. Variable represents the ref-
erence voltage,and
is the digital representation of .
All variables are normalized to the input voltage,
. Variable
is used as a feedforward term in (1). Note that by it-
self would give the correct duty cycle command for steady state
operation with constant load, if there were no load-dependent
voltage drop along the power train and no other nonidealities in
the output stage [2]. Design of digital PID control law is dis-
cussed in [3]–[5].
III. C
ONDITIONS FOR THE ELIMINATION OF LIMIT CYCLES
For the converter of Fig. 1, limit cycles refer to steady-state
oscillations of
and other system variables at frequencies
lower than the converter switching frequency
. Limit cy-
cles may result from the presence of signal amplitude quan-
tizers like the ADC and DPWM modules in the feedback loop.
Steady-state limit cycling may be undesirable if it leads to large,
unpredicted output voltage variations. Furthermore, since the
limit cycle amplitude and frequency are hard to predict, it is dif-
ficult to analyze and compensate for the resulting
noise
and the electro-magnetic interference (EMI) produced by the
converter.
Let us consider a system with ADC resolution of
bits
and DPWM resolution of
bits. For a buck converter, this
will correspond to voltage quantization of
steps for the ADC, and for the
0885-8993/03$17.00 © 2003 IEEE
302 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 1, JANUARY 2003
Fig. 1. Block diagram of a digitally controlled PWM buck converter.
DPWM. Fig. 2(a)
1
illustrates qualitatively the behavior of
in steady state when the DPWM resolution is less than
the ADC resolution, and there is no DPWM level that maps
into the ADC bin corresponding to the reference voltage
(this ADC bin will be referred to as the zero-error bin). In
steady state, the controller will be attempting to drive
to
the zero-error bin, however due to the lack of a DPWM level
there, it will alternate between the DPWM levels around the
zero-error bin. This results in nonequilibrium behavior, such as
steady-state limit cycling.
The first step toward eliminating limit cycles is to ensure that
under all circumstances there is a DPWM level that maps into
the zero-error bin. This can be guaranteed if the resolution of
the DPWM module is finer than the resolution of the ADC. A
one-bit difference in the resolutions,
, seems
sufficient in most applications since it provides two DPWM
levels per one ADC level
(4)
Yet, even if the above condition is met, limit cycling may
still occur if the feedforward term is not perfect and the con-
trol law has no integral term
. In this case, the con-
troller relies on nonzero error signal
to drive toward
the zero-error bin. However, once
is in the zero-error bin,
the error signal becomes zero, and
droops back below the
zero-error bin. This sequence repeats over and over again, re-
sulting in steady-state limit cycling. This problem can be solved
by the inclusion of an integral term in the control law. After a
transient, the integrator will gradually converge to a value that
drives
into the zero-error bin, where it will remain as long
as
, since a digital integrator is perfect [Fig. 2(b)]
(5)
An upper bound of unity is imposed on the integral gain, since
the digital integrator is intended to fine-tune the output voltage,
therefore it has to be able to adjust the duty cycle command by
steps as small as a least significant bit
.
1
In all simulations the data is sampled at the switching frequency, therefore
the switching ripple on
V
cannot be seen. For the discussions in this paper
the switching ripple is not of interest and its omission makes the plots clearer.
(a)
(b)
Fig. 2. Qualitative behavior of
V
with (a) DPWM resolution lower than the
ADC resolution and (b) DPWM resolution two times the ADC resolution and
with integral term included in control law.
Fig. 3(a) shows a simulation of the transient response of a dig-
itally controlled PWM converter. The resolution of the DPWM
module,
bits, is higher than the resolution of the
ADC,
bits, however steady-state limit cycling is ob-
served both before and after the load current step, since no in-
tegral term was used in the control law. On the other hand, in
Fig. 3(b) an integral term is added to the control law, and the
steady-state limit cycling is eliminated.
The two conditions suggested above are not sufficient for the
elimination of steady-state limit cycles, since the nonlinearity
of the quantizers in the feedback loop may still cause limit cy-
cling for high loop gains. Non-linear system analysis tools, such
as describing functions [5]–[7], can be used to determine the
maximum allowable loop gain not inducing limit cycles. The
PETERCHEV AND SANDERS: QUANTIZATION RESOLUTION AND LIMIT CYCLING 303
(a)
(b)
Fig. 3. Simulation of a DPWM converter output voltage under a load current
transient with integral term: (a) not included and (b) included in control law.
V
=5
V,
V
=1
:
5
V,
f
=250
kHz,
N
=9
b, and
N
=10
b.
feedback loop of the converter includes two quantizers—the
ADC and the DPWM—however in the present analysis we will
consider only the ADC nonlinearity, since it performs coarser
quantization if the DPWM resolution is made higher than that
of the ADC (as recommended above). The describing func-
tion of an ADC (a round-off quantizier) represents its effective
gain as a function of the input signal ac amplitude and dc bias.
When the control law contains an integral term, only limit cy-
cles that have zero dc component can be stable, because the
integrator drives the dc component of the error signal to the
zero-error bin. Since in steady state the dc bias is driven to
zero, and since the loop transmission,
, from the output
of the ADC to its input has a low-pass characteristic, the sinu-
soidal-input describing function of a round-off quantizer can be
used to analyze the stability of the system. The characteristic
of a round-off quantizer is plotted in Fig. 4(a), where
is the ADC input voltage, is the ADC quantization bin
size corresponding to one
, and is the quantized rep-
resentation of
. The corresponding describing function,
, is plotted in Fig. 4(b), where is the ac amplitude of
. From the plot it can be seen that the describing function
has a maximum value of about 1.3, corresponding to maximum
effective ADC gain. The control law (1), and hence
, can
then be designed to exclude limit cycles by ensuring that
Nyquist Criterion
(6)
holds for all nonzero finite signal amplitudes
and frequencies
. In practice, conventional loop design methods (e.g., Bode
plots) can be used, keeping in mind that the effective ADC gain
peaks somewhat above unity.
IV. C
ONTROLLED DIGITAL DITHER
The precision with which a digital controller regulates
is determined by the resolution of the ADC. In particular,
can be regulated with a tolerance of one of the ADC.
Many present-day applications, such as microprocessor VRMs,
demandregulationprecisionofabout10mV[8],requiringADCs
and DPWM modules with very high resolution. For example,
regulation resolution of 10 mV at
V corresponds
to ADC resolution of
V mV bits,
implyingDPWMresolutionofatleast
bitstoavoid
steady-state limit-cycling. For a converter switching frequency
of
MHz, such resolution would require a
GHz fast clock in a counter-comparator implementation of
the DPWM module, or
stages in a ring oscillator
implementation, resulting in high power dissipation or large
area [7], [9], [1]. Thus, it is beneficial to look for ways to use
low-resolution DPWM modules to achieve the desired high
resolution.
One method which can increase the effective resolution of
a DPWM module is dithering. It amounts to adding high-fre-
quency periodic or random signals to a certain quantized signal,
which is later filtered to produce averaged dc levels with in-
creased resolution. Analog dither has been used to increase the
effective resolution of a DPWM module [10]. However, analog
dither is difficult to generate and control, it is sensitive to analog
component variations, and it can be mixed only with analog sig-
nals in the converter, and not with signals inside a digital con-
troller. On the other hand, digital dither generated inside the
controller is simpler to implement and control, is insensitive
to analog component variations, and can offer more flexibility.
Therefore, the use of digital dither to improve the resolution of
DPWM modules is discussed in the present section.
A. Single-Phase Dither
The idea behind digital dither is to vary the duty cycle by
an
over a few switching periods, so that the average duty
cycle has a value between two adjacent quantized duty cycle
levels. The averaging action is implemented by the output
filter. The dither concept is illustrated in Fig. 5. Let and
correspond to two adjacent quantized duty cycle levels put
out by the DPWM module,
. If the duty
cycle is made to alternate between
and every next
304 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 1, JANUARY 2003
(a)
(b)
Fig. 4. Characteristic of: (a) a round-off quantizer and (b) the corresponding
describing function for sinusoidal signals with zero dc bias.
switching period, the average duty cycle over time will equal
. Thus, an intermediate
sub-bit level can be implemented by averaging over
two switching periods, resulting in an increase of the effective
DPWM resolution of 1 b. Using the same reasoning,
and levels can be implemented by averaging over
four switching periods (Fig. 6), which increases the effective
DPWM resolution by 2 b. Finally, it can be seen that by using
dither patterns spanning
switching periods, the effective
DPWM resolution can be increased by
b
(7)
where
is the hardware DPWM resolution, and
is the effective DPWM resolution.
B. Dither Patterns
Of course, the effective increase in DPWM resolution by
dithering does not come for free. The dithering of the duty
Fig. 5. Use of switching waveform dither to realize a
(1
=
2)
LSB
DPWM level
(1-b dither).
Fig. 6. Switching waveform dither patterns realizing
(1
=
4)
LSB
,
(1
=
2)
LSB
,
and
(3
=
4)
LSB
DPWM levels (2-b dither).
cycle creates an additional ac ripple at the output of the
filter, which is superimposed on the ripple from the converter
switching action. It is desirable to keep the amplitude of the
dither ripple low, in order to avoid poor output regulation,
EMI, and limit cycles (which may result from the interaction
between the dither ripple and the ADC). Thus it is beneficial to
select dither patterns that minimize the dither ripple.
For a dither sequence with a particular length (
switching
cycles for
-bit dither) there may be a few different dither pat-
terns that average to the same dc level. For example, in Fig. 6
the
level can be implemented with two different
sequences:
or .
The latter pattern has higher fundamental frequency, and thus
produces less output voltage ripple, due to the low-pass charac-
teristic of the output
filter.
Two sets of 3-b dither sequences are shown in Table I, with
“1” standing for the addition of an
to the duty cycle.
Table I(a) corresponds to a simple rectangular waveform dither
discussed in [11]. The generation of these patterns is very
systematic and thus easy to implement. On the other hand, the
dither sequences in Table I(b) were chosen with the aim of
minimizing their low frequency spectral content. Thus, when
filtered, they produce the lowest ripple for a given average duty
cycle. Notice that, while for the rectangular-waveform dither
the sequences producing lowest ripple are
0, 0, 0, 0, 0, 0, 0, 1
and its complement, for the minimum-ripple dither the ripple
produced by any sequence does not exceed the ripple produced
PETERCHEV AND SANDERS: QUANTIZATION RESOLUTION AND LIMIT CYCLING 305
by 0, 0, 0, 0, 0, 0, 0, 1 and its complement. Therefore, the
minimum-ripple sequences have a clear advantage over the
rectangular-waveform sequences, with respect to dither ripple
size.
Yet another dither generation approach is to use
modu-
lation, however it does not guarantee minimum-ripple patterns,
and further the dither spectral content is hard to predict.
modulation in power electronics applications is discussed, for
example, in [12] and [13].
C. Dither Generation Scheme
Fig. 7 shows a dither generation scheme that can produce
patterns of any shape, and can therefore implement minimum-
ripple dither such as the one in Table I(b). A look-up table stores
dither sequences, each b long, corresponding to the
sub-bit levels implemented with
-bit dither. The s
of the duty cycle command
select the dither sequence cor-
responding to the appropriate sub-bit level, while the
-bit
counter sweeps through this dither sequence. The dither pattern
is then added to the
sof to produce the duty cycle
command
which is sent to the hardware DPWM module.
D. Dither Ripple Size
In Section IV-A it was shown that the longer the dither pat-
terns used, the larger the effective DPWM resolution. However,
longer dither patterns can cause higher output ripple, since they
contain lower frequency components, and the
filter has less
attenuation at lower frequencies. This consideration puts a prac-
tical limit on the number of bits of dither that can be added to
increase the resolution of the DPWM module.
For the rectangular-waveform dither in Table I(a) some
simple mathematical analysis (see the Appendix) can give an
estimate of the maximum peak-to-peak ripple added to the
output voltage as a result of the dither
(8)
for
, and
(9)
for
, where is the fundamental frequency
of the dither
(10)
is the filter cutoff frequency, and is the zero
frequency associated with the output capacitor.
Once the amplitude of the dither is known, we can develop a
condition on howmanybits of dither,
, can be used in a certain
system, without inducing limit cycles (see the Appendix),
(11)
for
, and
(12)
TABLE I
3-B D
ITHER SEQUENCES
(a)
(b)
Fig. 7. Structure for adding arbitrary dither patterns to the duty cycle.
for , where
(13)
is the difference between the effective resolutions of the DPWM
and the ADC (in bits). For example, in Section III it was sug-
gested that making the resolution of the DPWM one bit higher
then that of the ADC adequately satisfies the condition to elimi-
nate steady-state limit cycling, hence
. The above equa-
tions can be used by starting with a guess for
, obtaining the
corresponding dither frequency from (10), and then using (11)
or (12), respectively, to obtain a bound on
. If the result is not
consistent with the initial guess for
, the procedure should be
repeated with a reduced value of
. On the other hand, if the
inequalities are satisfied, the value of
can be increased, and
the procedure can be repeated.