Proceedings ArticleDOI
Quasi-adiabatic 2×2 Barrel Shifter
Prasad D. Khandekar,Shaila Subbaraman,Venkat Raman Vinjamoori +2 more
- pp 321-324
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TLDR
In this article, the performance of Pass Transistor Adiabatic Logic (PAL) against that of static CMOS was analyzed in a cadence design environment using 180nm technology using cell based design approach.Abstract:
Demands for low power electronics have motivated designers to explore new approaches to VLSI circuits. The classical approaches of reducing energy dissipation in conventional CMOS circuits include reducing the supply voltages, node capacitances, and switching frequencies. Energy-recovery circuitry, on the other hand, is a new promising approach to the design of VLSI circuits with very low energy dissipation. Such circuits achieve low energy dissipation by restricting current to flow across devices with very low voltage drop and by recycling the energy stored on their capacitors. This paper analyzes the performance of Pass Transistor Adiabatic Logic (PAL) against that of static CMOS. A standard 2×2 Barrel Shifter is used as the benchmark circuit for comparison due to its modular design. The analysis is carried out in cadence design environment using 180nm technology using cell based design approach. The simulation is done at various operating voltages, frequencies, and load capacitances for each circuit family and technological node.read more
Citations
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Journal ArticleDOI
Design optimization of Reversible Logic Universal Barrel Shifter for Low Power applications
TL;DR: The objective of this work is to design a Universal Reversible Barrel Shifter that performs shifting left, right, rotates left and right and the performance characteristics are compared with respect to transistor cost, Garbage outputs and Quantum Cost.
Book ChapterDOI
Adiabatic Techniques for Energy-Efficient Barrel Shifter Design
TL;DR: This paper explains the design of a 4-bit Barrel shifter using two different adiabatic logics, namely positive feedback adiABatic logic (PFAL) and pass transistor adi Kabat- rigged logic (PAL).
Journal Article
Design of 32×32 Barrel Shifter Using VariousAdiabatic Techniques for Low PowerApplications
TL;DR: This paper gives a detailed account of 32 bit barrel shifter design using 3 techniques namely Differential Cascode voltage Switch Logic, Adiabatic Logic and Complementary Pass transistor AdiABatic Logic.
References
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Journal ArticleDOI
Low-power digital systems based on adiabatic-switching principles
TL;DR: The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation.
Journal ArticleDOI
An efficient charge recovery logic circuit
Yong Moon,Deog-Kyoon Jeong +1 more
TL;DR: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit and shows four to six times power reduction with a practical loading and operation frequency range.
Journal ArticleDOI
Pass-transistor adiabatic logic using single power-clock supply
TL;DR: In this article, a pass-transistor adiabatic logic (PAL) was proposed to operate from a single power-clock supply and outperforms the previously reported adiabilistic logic techniques in terms of its energy use.
Journal ArticleDOI
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
TL;DR: CAL is a dual-rail logic that operates from a single-phase AC power-clock supply that makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution.
Proceedings ArticleDOI
A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS
J.B. Burr,J. Shott +1 more
TL;DR: A CMOS test chip that includes a 1k-transistor self-testing encoder/decoder is verifiably error-free at supply voltages down to 20O mV, achieving 1/625 the power-delay product of standard 5 V CMOS.