Real-time detection of electrocardiogram wave features using template matching and implementation in FPGA
18 Mar 2015-International Journal of Biomedical Engineering and Technology (Inderscience Publishers)-Vol. 17, Iss: 3, pp 290-313
TL;DR: An algorithm for real–time detection of wave peaks and their features from single lead ECG data, which was implemented on Xilinx Spartan III Field Programmable Gate Array (FPGA) and clinically validated by medical expert.
Abstract: Electrocardiogram (ECG) can provide valuable clinical information on cardiac functions. This paper illustrates an algorithm for real–time detection of wave peaks and their features from single lead ECG data. At first, the ECG data was filtered for power line interference and high frequency noise. Then, a set of slope and polarity–based rule bases were generated from the first 6000 samples, which define templates of R–peak, P–and T–wave detection from the following beats. The algorithm was implemented on Xilinx Spartan III Field Programmable Gate Array (FPGA). For testing of the algorithm, ECG data was quantised at 8–bit resolution and delivered to the FPGA using synchronous transfer mechanism using parallel port of computer. Xilinx implementation results provided 97.58%, 98.4% and 97.78% detection sensitivity for P–, R– and T–waves, respectively. Different wave features (height, polarity and duration) were detected with an average error rate of 9.3%. The detected wave signatures were clinically validated by medical expert.
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TL;DR: This study presents a new field programmable gate array (FPGA)-based hardware implementation of the QRS complex detection, mainly based on the Pan and Tompkins algorithm, but applying a new, simple, and efficient technique in the detection stage.
Abstract: The continuous monitoring of cardiac patients requires an ambulatory system that can automatically detect heart diseases. This study presents a new field programmable gate array (FPGA)-based hardware implementation of the QRS complex detection. The proposed detection system is mainly based on the Pan and Tompkins algorithm, but applying a new, simple, and efficient technique in the detection stage. The new method is based on the centred derivative and the intermediate value theorem, to locate the QRS peaks. The proposed architecture has been implemented on FPGA using the Xilinx System Generator for digital signal processor and the Nexys-4 FPGA evaluation kit. To evaluate the effectiveness of the proposed system, a comparative study has been performed between the resulting performances and those obtained with existing QRS detection systems, in terms of reliability, execution time, and FPGA resources estimation. The proposed architecture has been validated using the 48 half-hours of records obtained from the Massachusetts Institute of Technology - Beth Israel Hospital (MIT-BIH) arrhythmia database. It has also been validated in real time via the analogue discovery device.
15 citations
TL;DR: In this paper, a resource efficient and low power architecture using Integer Haar Wavelet Transform (IHT) for the complete delineation of ECG signal has been presented, which uses single scale wavelet coefficients to delineate P-QRS-T features making it computationally simple.
6 citations
TL;DR: In this article , a resource efficient and low power architecture using Integer Haar Wavelet Transform (IHT) for the complete delineation of ECG signal has been presented, which uses single scale wavelet coefficients to delineate P-QRS-T features making it computationally simple.
4 citations
TL;DR: In this article, the use of SIMD components in Field-Programmable GAssembles has been studied for error-resilient programs intertwined with their quest for high throughput.
Abstract: The rapid evolution of error-resilient programs intertwined with their quest for high throughput has motivated the use of Single Instruction, Multiple Data (SIMD) components in Field-Programmable G...
2 citations
TL;DR: RAPID as mentioned in this paper is the first pipelined approximate multiplier and divider architecture, customized for FPGAs, which efficiently utilizes 6-input Look-up Tables (6-LUTs) and fast carry chains to implement Mitchell's approximate algorithms.
Abstract: The rapid updates in error-resilient applications along with their quest for high throughput have motivated designing fast approximate functional units for Field-Programmable Gate Arrays (FPGAs). Studies that proposed imprecise functional techniques are posed with three shortcomings: first, most inexact multipliers and dividers are specialized for Application-Specific Integrated Circuit (ASIC) platforms. Second, state-of-the-art (SoA) approximate units are substituted, mostly in a single kernel of a multi-kernel application. Moreover, the end-to-end assessment is adopted on the Quality of Results (QoR), but not on the overall gained performance. Finally, existing imprecise components are not designed to support a pipelined approach, which could boost the operating frequency/throughput of, e.g., division-included applications. In this paper, we propose RAPID, the first pipelined approximate multiplier and divider architecture, customized for FPGAs. The proposed units efficiently utilize 6-input Look-up Tables (6-LUTs) and fast carry chains to implement Mitchell's approximate algorithms. Our novel error-refinement scheme not only has negligible overhead over the baseline Mitchell's approach but also boosts its accuracy to 99.4% for arbitrary size of multiplication and division. Experimental results demonstrate the efficiency of the proposed pipelined and non-pipelined RAPID multipliers and dividers over accurate counterparts. Moreover, the end-to-end evaluations of RAPID, deployed in three multi-kernel applications in the domains of bio-signal processing, image processing, and moving object tracking for Unmanned Air Vehicles (UAV) indicate up to 45% improvements in area, latency, and Area-Delay-Product (ADP), respectively, over accurate kernels, with negligible loss in QoR.
1 citations
References
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01 Dec 2011
TL;DR: A reconfigurable architecture is proposed for real-time assessment of individual's health status based on development of a patient-specific health index and online analysis and fusion of multi-parameter physiological signals.
Abstract: A robust medical monitoring device should be able to provide intelligent diagnosis based on accurate analysis of physiological parameters in real-time. At the same time, such device must be able to adapt to the characteristics of a specific patient and desired diagnostic needs, and continue to operate even in presence of unexpected artifacts and accidental errors. A reconfigurable architecture is proposed for real-time assessment of individual's health status based on development of a patient-specific health index and online analysis and fusion of multi-parameter physiological signals. This is achieved by static configuration of processing elements and communication blocks in the architecture based on the patient's diagnostic needs. The proposed architecture is prototyped as a single integrated device on an FPGA platform and is evaluated using multi-parameter data from intensive care units (ICUs). Three representative test cases of concurrently analyzing Blood Pressure, Heart Rate, and Electrocardiogram (ECG) data from MIMIC database are presented. The results show the effectiveness of the proposed technique in eliminating false alarms caused by patient movements, monitor noise, or imperfections in the detection schemes.
22 citations
08 Feb 2012
TL;DR: The study reveals that Eigenvector method gives better performance in frequency domain for the ECG feature extraction.
Abstract: This paper discusses six most frequent methods used to extract different features in Electrocardiograph (ECG) signals namely Autoregressive (AR), Wavelet Transform (WT), Eigenvector, Fast Fourier Transform (FFT), Linear Prediction (LP), and Independent Component Analysis (ICA). The study reveals that Eigenvector method gives better performance in frequency domain for the ECG feature extraction.
21 citations
10 Nov 2011
TL;DR: This paper illustrates a simple algorithm for real time QRS detection from ECG data implemented on Xilinx field programmable gate array using very small number of memory cells.
Abstract: This paper illustrates a simple algorithm for real time QRS detection from ECG data. The algorithm is implemented on Xilinx field programmable gate array using very small number of memory cells. Single lead Synthetic ECG using ptb-db database (from Physionet) is generated from a personal computer using the parallel port (LPT1) at 1 ms sampling interval and delivered to the FPGA (Field Programmable Gate Array) board. At first, from the first 1500 samples, the QRS detection algorithm calculates some characteristic amplitude and slope based signatures which are used to form a rule base. These rules are used for detecting the next incoming QRS regions accurately. The index points of R-peaks are determined and shown in the LEDs using switch-based commands.
19 citations
18 Nov 2010
TL;DR: An Adaptive Lifting Scheme (ALS) has been developed and successfully implemented in Field Programmable Gate Array (FPGA) and its detection accuracy is higher than 99.681%, fulfilling ECG signal processing requirements.
Abstract: For ECG QRS complexes detection, an Adaptive Lifting Scheme (ALS) has been developed and successfully implemented in Field Programmable Gate Array (FPGA). Realized under XUP Virtex-II Pro environment, the system consists of Top Configuration Module, Detection module and ALS module. Tested by the samples generated from the MIT-BIH ECG Database, its detection accuracy is higher than 99.681%, fulfilling ECG signal processing requirements. Comparing with the same algorithm realized with C codes under TI's TMS320VC5509A DSP system, more than 20% of processing time is saved.
15 citations
14 Oct 2008
TL;DR: The algorithm and hardware architecture for the whole system of QRS Complex detection based on Mathematical Morphology and Quadratic Spline wavelet transform, with implementation in Field Programmable Gate Array (FPGA), is proposed.
Abstract: In recent years, algorithm based on Mathematical Morphology and wavelet transform has been proposed for ECG QRS Complex detection. However, its intensity of computation is high. This paper proposes the algorithm and hardware architecture for the whole system of QRS Complex detection based on Mathematical Morphology and Quadratic Spline wavelet transform, with implementation in Field Programmable Gate Array (FPGA). The system consists of Morphological filtering, Quadratic Spline wavelet transform and Modulus Maxima Pair Recognition modules. The parallel and pipelined architecture of system can operate in the maximum 35MHz with throughput of one sample per clock cycle. The QRS Complex detection accuracy for MIT/BIH arrhythmia database recordings and resource consumption are reported. The design is suitable for both batch processing of huge volume ECG data and real time applications for portable devices.
14 citations