scispace - formally typeset
Journal ArticleDOI

Real-Time SoC Security against Passive Threats Using Crypsis Behavior of Geckos

Reads0
Chats0
TLDR
This work seeks refuge to the crypsis behavior exhibited by geckos in nature to generate a runtime security technique for SoC architectures, which can bypass runtime passive threats of a HTH.
Abstract
The rapid evolution of the embedded era has witnessed globalization for the design of SoC architectures in the semiconductor design industry. Though issues of cost and stringent marketing deadlines have been resolved in such a methodology, yet the root of hardware trust has been evicted. Malicious circuitry, a.k.a. Hardware Trojan Horse (HTH), is inserted by adversaries in the less trusted phases of design. A HTH remains dormant during testing but gets triggered at runtime to cause sudden active and passive attacks. In this work, we focus on the runtime passive threats based on the parameter delay. Nature-inspired algorithms offer an alternative to the conventional techniques for solving complex problems in the domain of computer science. However, most are optimization techniques and none is dedicated to security. We seek refuge to the crypsis behavior exhibited by geckos in nature to generate a runtime security technique for SoC architectures, which can bypass runtime passive threats of a HTH. An adaptive security intellectual property (IP) that works on the proposed security principles is designed. Embedded timing analysis is used for experimental validation. Low area and power overhead of our proposed security IP over standard benchmarks and practical crypto SoC architectures as obtained in experimental results supports its applicability for practical implementations.

read more

Citations
More filters
Journal ArticleDOI

Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks

TL;DR: This work explores how power draining ability of HTHs may reduce lifetime of the system and an offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime ofThe system.
Journal ArticleDOI

Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components

TL;DR: Self-aware security modules attached with each IP works based on the Observe-Decide-Act paradigm and not only detects vulnerability but also organizes behavior of the IPs dynamically at runtime so that the high-level objective of task completion before a deadline is ensured.
Journal ArticleDOI

Hardware Trojan Mitigation in Pipelined MPSoCs

TL;DR: PMPGuard, a mechanism that detects the presence of hardware Trojans in Third Party Intellectual Property cores of PMPSoCs by continuous monitoring and testing and recovers the system by switching the infected processor core with another one, is presented.
Book ChapterDOI

SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans

TL;DR: A self aware approach for facilitating runtime security from integrity attacks or erroneous result generation due to HTHs is proposed, which overcomes the limitations of the existing redundancy based approach.
Proceedings ArticleDOI

Ensuring Green Computing in Reconfigurable Hardware based Cloud Platforms from Hardware Trojan Attacks

TL;DR: In this paper, the authors analyze how vulnerability in hardware like hardware trojan horses (HTH) can increment power dissipation suddenly at runtime, without affecting the basic security primitives like integrity, confidentiality or availability of the system.
References
More filters
Journal ArticleDOI

Hardware Trojans in Wireless Cryptographic ICs

TL;DR: Challenges related to detection for Trojans designed to leak secret information through the wireless channel are investigated and statistical analysis of the side-channel signals is proposed to help detect them.
Journal ArticleDOI

Embedded timing analysis: a soc infrastructure

TL;DR: This SoC infrastructure core is a flexible, scalable, and highly accurate embedded time interval analyzer (ETIA), used to measure a variety of timing-related SoC characteristics, including jitter.
Journal ArticleDOI

A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay

TL;DR: Simulations and FPGA results are used to demonstrate the effectiveness of the proposed clock-sweeping technique under process variations, even for Trojans as small as a few gates.
Journal ArticleDOI

Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation

TL;DR: This work proposes a novel application of key-based circuit structure and functionality obfuscation to achieve protection against hardware Trojans triggered by rare internal circuit conditions and shows that the scheme is capable of achieving high levels of security against Trojan attacks at modest area, power and delay overhead.
Proceedings ArticleDOI

Dynamic evaluation of hardware trust

TL;DR: This work explores an approach to this problem that combines multicore hardware with dynamic distributed software scheduling to determine hardware trust during in-field use at run time and dynamically achieves trust determination by identifying the existence of Trojans with a high level of confidence.
Related Papers (5)