Proceedings ArticleDOI
Reduction of crosstalk in mixed CNT bundle interconnects for high frequency 3D ICs and SoCs
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TLDR
In this article, the authors investigated the multi equivalent single conductor (MESC) model for mixed CNT bundles, which contains metallic single and double walled CNTs at the core and semiconducting single walled cNTs in the periphery.Abstract:
This paper investigates the multi equivalent single conductor (MESC) model for mixed CNT bundles (MCBs) which contains metallic single and double walled CNTs at the core and semiconducting single walled CNTs at the periphery. This structure shows the least delay due to crosstalk.read more
Citations
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Journal ArticleDOI
Future Dielectric Materials for CNT Interconnects - Possibilities and Challenges
TL;DR: In this article, a review of low-k dielectric materials for CNT interconnects is presented and the specific properties of these materials and the necessities for integrating them into CNT-interconnects to meet the requirements of future IC designers.
Proceedings ArticleDOI
Mixed CNT bundles as VLSI interconnects
TL;DR: In this paper, the performance analysis on SWCNT, DWCNT and Mixed CNT bundles as interconnects were done and it was shown that mixed CNT bundle is better in delay compared to SWNT bundle.
Journal ArticleDOI
Crosstalk Analysis of Triangular CNT Bundle Interconnects
TL;DR: In this paper, the authors analyzed and discussed the crosstalk behavior of triangular CNT bundle interconnects in two-line and three-line configurations, and the performance metrics that determine the functionality of the interconnect were found by HSPICE simulations.
Book ChapterDOI
Performance Analysis of Square and Triangular CNT Bundle Interconnects Driven by CNTFET-Based Inverters
TL;DR: In this paper, the authors proposed the use of triangular cross-sectioned CNT (T-CNT) bundle interconnects for VLSI circuits, which has the advantage of offering least possible crosstalk between adjacent interconnect.
Proceedings ArticleDOI
Analysis of triangular CNT bundle interconnects for current mode signalling
TL;DR: In this article, the authors proposed the use of triangular carbon nanotube bundles as VLSI interconnects for current mode signaling (CMS) in VLCI circuits, which have inherent advantages of lesser propagation delay and crosstalk delay than traditionally proposed square CNT bundle interconnect.
References
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Journal ArticleDOI
Surface Conductance Induced Dielectrophoresis of Semiconducting Single-Walled Carbon Nanotubes
TL;DR: In this article, the interaction between carbon nanotubes and the surfactant induces a nanotube surface conductance, which gives rise to a unique electric field frequency dependence of the nanotub dielectrophoresis.
Journal ArticleDOI
Single-Conductor Transmission-Line Model of Multiwall Carbon Nanotubes
TL;DR: In this article, the per-unit-length (p.u.l.) equivalent quantum capacitance and kinetic inductance of a multi-wall carbon nanotube (MWCNT) interconnect were derived analytically from the rigorous formulation of the complex multiconductor transmission-line propagation equations.
Journal ArticleDOI
Crosstalk Prediction of Single- and Double-Walled Carbon-Nanotube (SWCNT/DWCNT) Bundle Interconnects
TL;DR: In this article, the authors investigated the crosstalk effects in single and double-walled carbon-nanotube (SWCNT and DWCNT) bundle-interconnect architectures.
Journal ArticleDOI
Fast Transient Analysis of Next-Generation Interconnects Based on Carbon Nanotubes
TL;DR: In this article, the time-domain analysis of CMOS gates driving next-generation interconnects consisting of single wall carbon nanotube (SWCNT) bundles or multiwall carbon nanotideubes (MWCNTs) is carried out.
Journal ArticleDOI
Modeling of Crosstalk Effects in Multiwall Carbon Nanotube Interconnects
Feng Liang,Gaofeng Wang,Hai Lin +2 more
TL;DR: In this article, the worst case time delay and peak crosstalk voltage on victim wire of multi-wire carbon nanotube (MWCNT) interconnect configurations are derived and compared to those of the copper (Cu) wire counterparts for the intermediate and global interconnects at the 22-and 14-nm technology nodes.
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