Reduction of testing power with pulsed scan flip-flop for scan based testing
Citations
8 citations
Cites background from "Reduction of testing power with pul..."
...Conventional Single-Edge-Triggered Flip-Flops To improve the performance of a conventional Transmission Gate Flip-Flop (TGFF shown in Figure 1) [34], [35], an inverter and transmission gate is added in [36] between the output of master latch and the output of slave latch to accomplish a push–pull effect at the slave latch....
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8 citations
Cites background or methods from "Reduction of testing power with pul..."
...The circuit/clock modification [2], [3], [4], [5], [6] based technique are proposed by various research groups to reduce the test power....
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...This includes clock gating [3], scan enable disabling [4], virtual circuit partitioning [5], scan cell modification [6]....
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6 citations
6 citations
Cites methods from "Reduction of testing power with pul..."
...Also many techniques such as [7-8], [14] were proposed to reduce the test power in scan based testing....
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4 citations
Cites background from "Reduction of testing power with pul..."
...1) [3, 4], addition of an inverter and transmission gate between the outputs of master and slave latches to accomplish a push–pull effect at the slave latch, was proposed in [5]....
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...[3] D....
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References
660 citations
550 citations
"Reduction of testing power with pul..." refers background in this paper
...low power VLSI circuits has become an important issue [ 12 ]....
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...and wireless communication systems requires low power VLSI circuits [ 12 ]....
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516 citations
"Reduction of testing power with pul..." refers background in this paper
...Minimizing power dissipation during the VLSI design flow increases lifetime and reliability of the circuit [13,14]....
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...Numerous techniques for low power VLSI circuit design were reported [13] for CMOS technology where the dominant factor of power dissipation is dynamic power dissipation caused by switching activity [14]....
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285 citations
183 citations
"Reduction of testing power with pul..." refers background in this paper
...Testing power may be twice as high as the power consumed during normal function mode [7], because: Successive functional input vectors usually have significant correlations than the correlations between consecutive test patterns....
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