scispace - formally typeset
Search or ask a question
Proceedings ArticleDOI

Reduction of testing power with pulsed scan flip-flop for scan based testing

TL;DR: Experimental results on ISCAS89 benchmark circuit show that the proposed scan flip-flop can be used to reduce the test power.
Abstract: In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops (Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using ELDO simulator with TSMC 180 nm CMOS technology. Based on this evaluation, pulsed triggered flip-flop is selected as scan flip-flop because of lower transition power. Comparison of proposed scan flip-flop with existing mux based master-slave scan flip-flop is performed at the layout level. Experimental results on ISCAS89 benchmark circuit show that the proposed scan flip-flop can be used to reduce the test power.
Citations
More filters
Journal ArticleDOI
TL;DR: In this paper, the proposed flip-flop has state retention property to save power and to switch circuit between idle and active modes smoothly, and the feedback path is also improved to decrease power dissipation.
Abstract: In this paper, the proposed flip-flop reduces power consumption by reducing the clock switching power that was wasted otherwise. Unlike many other gated flip-flops, the proposed gated flip-flop has state retention property to save power and to switch circuit between idle and active modes smoothly. The feedback path is also improved in the proposed flip-flop to decrease power dissipation. The proposed clock-gating scheme only requires 4 transistors, thus occupies the small silicon area. Further, the proposed clock gating network can be shared among a group of flip-flops to reduce the power and area overhead of the gating network. The simulation results show that for all supply voltages, the proposed flip-flop has the least power dissipation among all the designs for low switching activities. The proposed flip-flop has up to 7.82 times power improvement than the existing flip-flops. However, for 100% data activity, the proposed FF consumes up to 2.71 times power than the existing flip-flops. The proposed clock gated flip-flop structure is best suited for applications where input signal switching activity is low and speed is not a crucial factor.

8 citations


Cites background from "Reduction of testing power with pul..."

  • ...Conventional Single-Edge-Triggered Flip-Flops To improve the performance of a conventional Transmission Gate Flip-Flop (TGFF shown in Figure 1) [34], [35], an inverter and transmission gate is added in [36] between the output of master latch and the output of slave latch to accomplish a push–pull effect at the slave latch....

    [...]

Proceedings ArticleDOI
19 Dec 2012
TL;DR: A new X-filling technique to reduce the shift and capture transitions occurred during scan based test application using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced.
Abstract: In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.

8 citations


Cites background or methods from "Reduction of testing power with pul..."

  • ...The circuit/clock modification [2], [3], [4], [5], [6] based technique are proposed by various research groups to reduce the test power....

    [...]

  • ...This includes clock gating [3], scan enable disabling [4], virtual circuit partitioning [5], scan cell modification [6]....

    [...]

Proceedings ArticleDOI
29 Apr 2013
TL;DR: A Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss and to get the required tradeoff, an adaptive type technique is utilizing.
Abstract: Power reduction during testing is an important concern in scan based tests. But methods to reduce shift power will results in test coverage loss. So a Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss. To get the required tradeoff, an adaptive type technique is utilizing where the previous test responses are given as feedback to a transition controller which is capable of generating highly correlated test patterns. The experimental results on ISCAS'89 benchmark circuits' shows efficiency of the work in terms of reduction in test power.

6 citations

01 Jan 2013
TL;DR: A test data compression and decompression scheme using reconfigurable multipliers that reduces significant hardware by exploiting the advantage of using the existing circuitry in the circuit under test for decompression and improves encoding efficiency.
Abstract: One of the increasingly difficult challenges in testing System-On-a-Chip (SoC) is dealing with the large amount of test vectors that must be stored in the tester and transferred between the testers. The test data bandwidth between the tester and the SOC is a bottleneck that can result in long test times when testing complex SOCs that contain many cores. Hence a test data compression and decompression scheme using reconfigurable multipliers has been presented in this paper. This scheme stores test vectors as a product of two deterministic vector seeds and uses the intermediate states of the multiplication of the vector seeds using the reconfigurable serial multiplier, to realize the test vector. Since multipliers are one of the widely used components in many SOCs, this method reduces significant hardware by exploiting the advantage of using the existing circuitry in the circuit under test for decompression. It provides a twofold advantage by reducing the amount of test data that needs to be stored on the tester and reducing the time for transferring test data from the tester to the circuit-under-test resulting in better encoding efficiency. Linear decompression with free variables is used. The encoding efficiency could be further explored with high percent of free variables. This scheme works best for circuits within built multipliers and significant reduction in hardware is observed. Experimental results obtained with ISCAS'89 benchmark shows the efficiency of this scheme on reduction of test data volume as well as the test time.

6 citations


Cites methods from "Reduction of testing power with pul..."

  • ...Also many techniques such as [7-8], [14] were proposed to reduce the test power in scan based testing....

    [...]

Journal Article
TL;DR: The proposed flip-flop is the best energy efficient with the comparable power delay product (PDP) having an improvement of up to 61.53% in view of power consumption.
Abstract: In this work, a new area and power efficient single edge triggered flip-flop has been proposed. The proposed design is compared with six existing flip-flop designs. In the proposed design, the number of transistors is reduced to decrease the area. The number of clocked transistors of the devised flip-flop is also reduced to minimize the power consumption. As compared to the other state of the art single edge triggered flip-flop designs, the newly proposed design is the best energy efficient with the comparable power delay product (PDP) having an improvement of up to 61.53% in view of power consumption. The proposed flip-flop also has the lowest transistor count and the lowest area. The simulation results show that the proposed flip-flop is best suited for low power and low area systems especially for low data activity and high frequency applications. Keywords: PDP, reliability, delay, process node, clock frequency

4 citations


Cites background from "Reduction of testing power with pul..."

  • ...1) [3, 4], addition of an inverter and transmission gate between the outputs of master and slave latches to accomplish a push–pull effect at the slave latch, was proposed in [5]....

    [...]

  • ...[3] D....

    [...]

References
More filters
Journal ArticleDOI
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Abstract: In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.

660 citations

Journal ArticleDOI
TL;DR: An in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems is presented and the many issues facing designers at architectural, logical, and physical levels of design abstraction are described.
Abstract: Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

550 citations


"Reduction of testing power with pul..." refers background in this paper

  • ...low power VLSI circuits has become an important issue [ 12 ]....

    [...]

  • ...and wireless communication systems requires low power VLSI circuits [ 12 ]....

    [...]

Book
01 Jan 2000
TL;DR: Low--Power CMOS VLSI Design and Test of Low--Voltage CMOS Circuits and Low--Energy Computing Using Energy Recovery Techniques.
Abstract: Low--Power CMOS VLSI Design. Physics of Power Dissipation in CMOS FET Devices. Power Estimation. Synthesis for Low Power. Design and Test of Low--Voltage CMOS Circuits. Low--Power Static Ram Architectures. Low--Energy Computing Using Energy Recovery Techniques. Software Design for Low Power. Index.

516 citations


"Reduction of testing power with pul..." refers background in this paper

  • ...Minimizing power dissipation during the VLSI design flow increases lifetime and reliability of the circuit [13,14]....

    [...]

  • ...Numerous techniques for low power VLSI circuit design were reported [13] for CMOS technology where the dominant factor of power dissipation is dynamic power dissipation caused by switching activity [14]....

    [...]

Proceedings ArticleDOI
26 Oct 2004
TL;DR: Case study information on ATPG- and DFT-based solutions for test power reduction is presented and ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test.
Abstract: It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.

285 citations

Proceedings ArticleDOI
01 May 2005
TL;DR: Experimental results show the effectiveness of the novel low-capture-power X-filling method in reducing capture power dissipation without any impact on area, timing, and fault coverage.
Abstract: Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0's and 1's to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.

183 citations


"Reduction of testing power with pul..." refers background in this paper

  • ...Testing power may be twice as high as the power consumed during normal function mode [7], because: Successive functional input vectors usually have significant correlations than the correlations between consecutive test patterns....

    [...]