Reliability-aware design for nanometer-scale devices
David Atienza,G. De Micheli,Luca Benini,José L. Ayala,P.G. Del Valle,Michael DeBole,Vijaykrishnan Narayanan +6 more
- pp 549-554
Reads0
Chats0
TLDR
This paper illustrates with a case study of an embedded processor that effective reliability-aware design can be achieved in nanometer-scale devices through integral design approaches that covers modeling and exploration of reliability effects, and hardware-software architectural techniques to provide reliability-enhanced solutions at both microarchitectural- and system-level.Abstract:
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges to maintain manufacturing yield rates and reliable devices in their expected lifetimes for latest nanometer-scale dimensions. In fact, new system and processor microarchitectures require new reliability-aware design methods and exploration tools that can face these challenges without significantly increasing manufacturing cost, reducing system performance or imposing large area overheads due to redundancy. In this paper we overview the latest approaches in reliability modeling and variability-tolerant design for latest technology nodes, and advocate the need of reliability- aware design for forthcoming consumer electronics. Moreover, we illustrate with a case study of an embedded processor that effective reliability-aware design can be achieved in nanometer-scale devices through integral design approaches that covers modeling and exploration of reliability effects, and hardware-software architectural techniques to provide reliability-enhanced solutions at both microarchitectural- and system-level.read more
Citations
More filters
Journal ArticleDOI
Hardware/Software Codesign: The Past, the Present, and Predicting the Future
TL;DR: This paper presents major achievements of two decades of research on methods and tools for hardware/software codesign by starting with a historical survey of its roots, highlighting its major research directions and achievements until today, and predicting in which direction research in codesign might evolve in the decades to come.
Proceedings ArticleDOI
Dynamic thermal management in 3D multicore architectures
TL;DR: This work first investigates how the existing thermal management, power management and job scheduling policies affect the thermal behavior in 3D chips, and proposes a dynamic thermally-aware job scheduling technique for 3D systems to reduce the thermal problems at very low performance cost.
Journal ArticleDOI
Utilizing Predictors for Efficient Thermal Management in Multiprocessor SoCs
TL;DR: This paper investigates how to use predictors for forecasting temperature and workload dynamics, and proposes proactive thermal management techniques for multiprocessor system-on-chips.
Journal ArticleDOI
Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach
TL;DR: How output error probabilities change with increasing number of simultaneous faults is shown and the results obtained show that output error probability resulting from multiple-event transient or multiple-bit upsets can vary across different outputs and different circuits by several orders of magnitude.
Proceedings ArticleDOI
Proactive temperature management in MPSoCs
TL;DR: This work proposes a proactive thermal management approach, which estimates the future temperature using regression, and allocates workload on a multicore system to reduce and balance the temperature to avoid temperature induced problems.
References
More filters
Proceedings ArticleDOI
MiBench: A free, commercially representative embedded benchmark suite
Matthew R. Guthaus,Jeff Ringenberg,Daniel J. Ernst,Todd Austin,Trevor Mudge,Richard B. Brown +5 more
TL;DR: A new version of SimpleScalar that has been adapted to the ARM instruction set is used to characterize the performance of the benchmarks using configurations similar to current and next generation embedded processors.
Journal ArticleDOI
Designing reliable systems from unreliable components: the challenges of transistor variability and degradation
TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
Journal ArticleDOI
Temperature-aware microarchitecture: Modeling and implementation
Kevin Skadron,Mircea R. Stan,Karthik Sankaranarayanan,Wei Huang,Sivakumar Velusamy,David Tarjan +5 more
TL;DR: HotSpot is described, an accurate yet fast and practical model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package that shows that power metrics are poor predictors of temperature, that sensor imprecision has a substantial impact on the performance of DTM, and that the inclusion of lateral resistances for thermal diffusion is important for accuracy.
Journal ArticleDOI
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
TL;DR: A methodology to statistically design the SRAM cell and the memory organization using the failure-probability and the yield-prediction models and can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.
Journal ArticleDOI
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
TL;DR: A complete simulation platform for a multi-processor systems-on-chip called MP-ARM is developed, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication architecture, memory models and support for parallel programming.