Journal ArticleDOI
Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks
Andreas Kerber,Eduard A. Cartier +1 more
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TLDR
In this paper, the authors summarized recent advances in the understanding of charge trapping and defect generation in HfO2/TiN gate stacks and discussed test procedures specifically tailored to quantify gate stack reliability.Abstract:
It has been demonstrated that the introduction of HfO2/ TiN gate stacks into CMOS technologies provides the means to continue with traditional device gate length scaling. However, the introduction of HfO2 as a new gate dielectric and TiN as a metallic gate electrode into the gate stack of FETs brings about new challenges for understanding reliability physics and qualification. This contribution summarizes recent advances in the understanding of charge trapping and defect generation in HfO2/ TiN gate stacks. This paper relates the electrical properties to the chemical/physical properties of the high-epsiv dielectric and discusses test procedures specifically tailored to quantify gate stack reliability of HfO2/TiN gate stacks.read more
Citations
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Journal ArticleDOI
High-K materials and metal gates for CMOS applications
John Robertson,Robert M. Wallace +1 more
TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Journal ArticleDOI
Towards CMOS-compatible nanophotonics: Ultra-compact modulators using alternative plasmonic materials
Viktoriia E. Babicheva,Nathaniel Kinsey,Gururaj V. Naik,Marcello Ferrera,Andrei V. Lavrinenko,Vladimir M. Shalaev,Alexandra Boltasseva +6 more
TL;DR: It is shown that an extinction ratio of 46 dB/µm can be achieved, allowing for a 3-dB modulation depth in much less than one micron at the telecommunication wavelength.
Journal ArticleDOI
Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?
TL;DR: High precise IL thickness control in an ultra-thin IL regime (<0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.
Journal ArticleDOI
Examining nanophotonics for integrated hybrid systems: a review of plasmonic interconnects and modulators using traditional and alternative materials [Invited]
TL;DR: It is suggested that nanophotonic technologies offer key advantages for future hybrid electrophotonic devices, where the movement toward new material platforms is a precursor to high-performance, industry-ready devices.
Journal ArticleDOI
Enhancing ferroelectricity in dopant-free hafnium oxide
Ashish Pal,Vijay K. Narasimhan,Stephen L. Weeks,Karl A. Littau,Dipankar Pramanik,Tony P. Chiang +5 more
TL;DR: In this article, the oxidant dose was controlled to promote ferroelectricity in dopant-free ALD hafnium oxide films, and the results showed that the reduction of the dose gave a sixfold improvement in remanent polarization.
References
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Journal ArticleDOI
Band offsets of wide-band-gap oxides and implications for future electronic devices
TL;DR: In this paper, the Schottky barrier heights and band offsets for high dielectric constant oxides on Pt and Si were calculated and good agreement with experiment is found for barrier heights.
Journal ArticleDOI
High dielectric constant gate oxides for metal oxide Si transistors
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Proceedings ArticleDOI
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Journal ArticleDOI
Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-κ insulator: The role of remote phonon scattering
TL;DR: In this paper, the dispersion of the interfacial coupled phonon-plasmon modes, their electron-scattering strength, and their effect on the electron mobility for Si-gate structures were investigated.
Journal ArticleDOI
New insights in the relation between electron trap generation and the statistical properties of oxide breakdown
Robin Degraeve,Guido Groeseneken,R. Bellens,J. L. Ogier,M. Depas,Philippe Roussel,Herman Maes +6 more
TL;DR: In this paper, a percolation-based model for intrinsic breakdown in thin oxide layers is proposed, which can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q/sub BD/-distribution for ultrathin oxides.