Journal ArticleDOI
Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs
Keheng Huang,Yu Hu,Xiaowei Li +2 more
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TLDR
This paper proposes a novel reliability-oriented placement and routing algorithm that combines both the fault occurrence probability and the error propagation probability together to enhance system-level robustness against soft errors.Abstract:
As the feature size shrinks to the nanometer scale, SRAM-based FPGAs will become increasingly vulnerable to soft errors Existing reliability-oriented placement and routing approaches primarily focus on reducing the fault occurrence probability (node error rate) of soft errors However, our analysis shows that, besides the fault occurrence probability, the propagation probability (error propagation probability) plays an important role and should be taken into consideration In this paper, we first propose a cube-based analysis algorithm to efficiently and accurately estimate the error propagation probability Based on such a model, we propose a novel reliability-oriented placement and routing algorithm that combines both the fault occurrence probability and the error propagation probability together to enhance system-level robustness against soft errors Experimental results show that, compared with the baseline versatile place and route technique, the proposed scheme can reduce the failure rate by 2073%, and increase the mean time between failures by 3944%read more
Citations
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Journal ArticleDOI
Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits
TL;DR: A new approach for analyzing the propagation probabilities of SET in logic circuits by considering three fault masking effects, matrix union operations and SET Propagation Probabilities Matrices is presented.
Journal ArticleDOI
Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults
TL;DR: A novel soft error reliability calculation approach for logic circuits based on a probability distribution model that can obtain an accurate reliability range through single fault and double faults simulations with small sample sizes, and also scales well with the variation of the error rate of the circuit element.
Journal ArticleDOI
Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch
TL;DR: A hardware implementation of a manager that applies these techniques at runtime and steers the execution of the running TGs is presented, demonstrating that the required runtime computations can be carried out in negligible delays.
Proceedings ArticleDOI
DAVOS: EDA Toolkit for Dependability Assessment, Verification, Optimisation and Selection of Hardware Models
TL;DR: DAOS is presented, an EDA toolkit supporting assessment, verification, optimisation (design space exploration), and selection (benchmarking) processes for dependability-aware hardware implementations and underlying implementation and analysis phases can be customized to consider alternative off-the-self languages, tools, components and technologies from a dependability perspective.
Journal ArticleDOI
Hybrid scheduling to enhance reliability of real-time tasks running on reconfigurable devices
TL;DR: Experimental results show that the hybrid scheduling technique enhances the mean-time-to-failure of the system by an average factor of 1.22 in comparison with a similar state-of-the-art study.
References
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Book ChapterDOI
VPR: A new packing, placement and routing tool for FPGA research
Vaughn Betz,Jonathan Rose +1 more
TL;DR: In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
Journal ArticleDOI
Single event upset at ground level
TL;DR: In this paper, ground level upsets have been observed in computer systems containing large amounts of random access memory (RAM). Atmospheric neutrons are most likely the major cause of the upsets based on measured data using the Weapons Neutron Research (WNR) neutron beam.
Journal ArticleDOI
Random Pattern Testability
TL;DR: A new analytical method of computing the fault coverage that is fast compared with simulation is described that is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault Coverage of the random test.
Proceedings ArticleDOI
Critical Path Tracing - An Alternative to Fault Simulation
TL;DR: This work presents an alternative to fault simulation, referred to as critical path tracing, that determines the faults detected by a set of tests using a backtracing algorithm starting at the primary outputs of a circuit.
Journal ArticleDOI
A new reliability-oriented place and route algorithm for SRAM-based FPGAs
Luca Sterpone,Massimo Violante +1 more
TL;DR: A reliability-oriented place and route algorithm is presented that is able to effectively mitigate the effects of the considered faults and is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique.