Removal of threading dislocations from patterned heteroepitaxial semiconductors by glide to sidewalls
01 Nov 1998-Journal of Electronic Materials (The Metals, Minerals, and Materials Society)-Vol. 27, Iss: 11, pp 1248-1253
TL;DR: In this article, the authors show that threading dislocations can be removed from patterned heteroepitaxial semiconductors by glide to the sidewalls, which is driven by the presence of image forces.
Abstract: We have shown that threading dislocations can be removed from patterned heteroepitaxial semiconductors by glide to the sidewalls, which is driven by the presence of image forces. In principle, it should be possible to attain highly mismatched heteroepitaxial semiconductors which are completely free from threading dislocations, even though they are not pseudomorphic, by patterned heteroepitaxial processing. There are two basic approaches to patterned heteroepitaxial processing. The first involves selective area growth on a pre-patterned substrate. The second approach involves post-growth patterning followed by annealing. We have developed a quantitative model which predicts that there is a maximum lateral dimension for complete removal of threading dislocations by patterned heteroepitaxy. According to our model, this maximum lateral dimension is proportional to the layer thickness and increases monotonically with the lattice mismatch. For heteroepitaxial materials with greater than 1% lattice mismatch, our model predicts that practical device-sized threading dislocation-free regions may be realized by patterned heteroepitaxial processing.
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Patent•
TSMC1
TL;DR: In this paper, the fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations is discussed.
Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
326 citations
TL;DR: In this article, a defect-free germanium was demonstrated in SiO2 trenches on silicon via aspect ratio trapping, whereby defects arising from lattice mismatch are trapped by laterally confining sidewalls.
Abstract: Defect-free germanium has been demonstrated in SiO2 trenches on silicon via Aspect Ratio Trapping, whereby defects arising from lattice mismatch are trapped by laterally confining sidewalls. Results were achieved through a combination of conventional photolithography, reactive ion etching of SiO2, and selective growth of Ge as thin as 450nm. Full trapping of dislocations originating at the Ge∕Si interface has been demonstrated for trenches up to 400nm wide without the additional formation of defects at the sidewalls. This approach shows great promise for the integration of Ge and/or III-V materials, sufficiently large for key device applications, onto silicon substrates.
228 citations
Patent•
13 Jun 2008TL;DR: In this paper, a dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer is formed above a buffer layer having a lattice constant similar to a InP.
Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.
190 citations
Patent•
TSMC1
TL;DR: In this paper, an aspect ratio trapping approach is used to reduce defects in a semiconductor lattice lattice formed by removing a portion of dielectric layer to expose a side portion of the crystalline material and defining a gate thereover.
Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
186 citations
TL;DR: In this paper, the authors review recent advances in the field of quantum dot lasers on silicon and present a summary of device performance, reliability, and comparison with similar quantum well lasers grown on silicon.
Abstract: We review recent advances in the field of quantum dot lasers on silicon. A summary of device performance, reliability, and comparison with similar quantum well lasers grown on silicon will be presented. We consider the possibility of scalable, low size, weight, and power nanolasers grown on silicon enabled by quantum dot active regions for future short-reach silicon photonics interconnects.
143 citations
References
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Book•
01 Jan 1965
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TL;DR: In this article, the authors have grown compositionally graded GexSi1−x layers on Si at 900 °C with both molecular beam epitaxy and rapid thermal chemical vapor deposition techniques.
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744 citations
TL;DR: In this paper, the authors investigated the effect of growth area on interface dislocation density in strained-layer epitaxy and fabricated 2-μm-high mesas of varying lateral dimensions and geometry in (001) GaAs substrates with dislocation densities of 1.5×105, 104, and 102 cm−2.
Abstract: To investigate the effect of growth area on interface dislocation density in strained‐layer epitaxy, we have fabricated 2‐μm‐high mesas of varying lateral dimensions and geometry in (001) GaAs substrates with dislocation densities of 1.5×105, 104, and 102 cm−2. 3500‐, 7000‐, and 8250‐A‐thick In0.05Ga0.95As layers, corresponding to 5, 10, and 11 times the experimental critical layer thickness as measured for large‐area samples, were then deposited by molecular‐beam epitaxy. For the 3500‐A layers, the linear interface dislocation density, defined as the inverse of the average dislocation spacing, was reduced from greater than 5000 to less than 800 cm−1 for mesas as large as 100 μm. A pronounced difference in the linear interface dislocation densities along the two interface 〈110〉 directions indicates that α dislocations nucleate about twice as much as β dislocations. For samples grown on the highest dislocation density substrates, the linear interface‐dislocation density was found to vary linearly with mesa...
326 citations
IBM1
TL;DR: In this article, a simple theoretical model and experimental observations made on deposits of Ga(As, P) on GaAs, suggest that it is desirable for the film thickness to be small.
300 citations