Resolving horizontal constraints and minimizing net wire length for multi-layer channel routing
19 Oct 1993-Vol. 1, pp 569-573
TL;DR: This paper proposes an O(m + d/sub max/log d/ sub max/) time algorithm for minimizing the total net wire length in the V/sub i+1/H/ sub i/ (i/spl ges/1) routing model, where the horizontal and vertical layers of interconnect alternate.
Abstract: The channel routing problem in VLSI design is to route a specified interconnection among modules in as small an area as possible. Hashimoto and Stevens (1971) proposed an algorithm for solving the two-layer channel routing problem in the absence of vertical constraints. In this paper, we analyze this algorithm in two different ways. In the first analysis, we show that a graph-theoretic realization, algorithm MCC1, runs in O(m + n + e) time, where m is the size of the channel specification of n nets, and e is the size of the complement of the horizontal constraint graph. In the second analysis, algorithm MCC2, we show that a time complexity of O(m + n log n) can be achieved. Algorithms MCC1 and MCC2 guarantee optimum routing solutions under the multi-layer V/sub i+1/H/sub i/ (i/spl ges/1) routing model, where the horizontal and vertical layers of interconnect alternate. Finally, we consider the problem of minimizing the total net wire length in the V/sub i+1/H/sub i/ (i/spl ges/1) routing model. Given a channel specification and a partition of the set of nets (where the nets within each part of the partition are non-overlapping), we propose an O(m + d/sub max/log d/sub max/) time algorithm for minimizing the total net wire length, subject to the condition that nets from a part of the partition are assigned to the same track. All our solutions use the minimum number of via holes. >
Citations
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04 Jan 1995
TL;DR: A general framework for viewing a class of heuristics for track assignment in channel routing from a purely graph theoretic angle is proposed and an algorithm for minimizing the total wire length in the two-layer VH and three-layer HVH routing models is designed.
Abstract: In this paper we propose a general framework for viewing a class of heuristics for track assignment in channel routing from a purely graph theoretic angle. Within this framework we propose algorithms for computing routing solutions using optimal or near optimal number of tracks for several well-known benchmark channels in the two-layer VH. Three-layer HVH, and multi-layer V/sub i/H/sub i/ and V/sub i/H/sub i+1/ routing models. Within the same framework we also design an algorithm for minimizing the total wire length in the two-layer VH and three-layer HVH routing models.
20 citations
Patent•
11 Jan 1999Abstract: A line capacitance is estimated in consideration of an influence of an adjacent line in rough routing, so that line paths can be determined so as to be free from a timing error. A routing graph is generated from a target integrated circuit, and line paths of cell-to-cell lines are initially determined on the basis of a passage cost set with regard to each of edges of the routing graph. With regard to each edge of the routing graph, the number of cell-to-cell lines passing through the edge is obtained as a line density, and a line capacitance of each line path in view of the influence of an adjacent line is estimated on the basis of the line density. It is verified whether or not there is a timing error with a delay time estimated, and when the integrated circuit does not satisfy a predetermined timing constraint, the line paths are re-determined with the passage cost of each edge allowed to be affected by the line capacitance. Alternatively, allocation to an interconnect layer is changed or a line-to-line distance is increased, so that the integrated circuit can satisfy the timing constraint.
9 citations
01 Jan 2006
TL;DR: This paper has developed heuristic algorithms for computing reduced crosstalk two-layer channel routing solutions for simplest as well as general channel instances and the results obtained are highly encouraging.
Abstract: Crosstalk minimization is one of the most important high performance aspects in interconnecting VLSI circuits. With advancement of fabrication technology, devices and interconnecting wires are placed in closer proximity and circuits operate at higher frequencies. This results in crosstalk between wire segments. Crosstalk minimization problem for the reserved two-layer Manhattan channel routing is NP-hard, even if the channel instances are free from any vertical constraint (simplest channel instances). In this paper we have developed heuristic algorithms for computing reduced crosstalk two-layer channel routing solutions for simplest as well as general channel instances. In general, the results obtained are highly encouraging.
8 citations
10 Jun 2011
TL;DR: This paper develops an efficient heuristic algorithm for appreciably reducing the total wire length in the reserved two-layer no-dogleg Manhattan channel routing model and results obtained are greatly encouraging.
Abstract: Minimization of total (vertical) wire length is one of the most important problems in laying out blocks in VLSI physical design. Minimization of wire length not only reduces the cost of physical wiring required, but also reduces the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delays. Since the problem of computing minimum wire length routing solutions in no-dogleg, two-layer channel routing is NP-hard, it is interesting to develop heuristic algorithms that compute routing solutions of as low total (vertical) wire length as possible. In this paper we develop an efficient heuristic algorithm for appreciably reducing the total wire length in the reserved two-layer no-dogleg Manhattan channel routing model. Experimental results obtained are greatly encouraging.
7 citations
TL;DR: A deterministic polynomial time algorithm is proposed that computes a better and non-trivial lower bound on the number of tracks required for routing a channel without doglegging.
7 citations
References
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Book•
01 Jan 1980
TL;DR: This new Annals edition continues to convey the message that intersection graph models are a necessary and important tool for solving real-world problems and remains a stepping stone from which the reader may embark on one of many fascinating research trails.
Abstract: Algorithmic Graph Theory and Perfect Graphs, first published in 1980, has become the classic introduction to the field. This new Annals edition continues to convey the message that intersection graph models are a necessary and important tool for solving real-world problems. It remains a stepping stone from which the reader may embark on one of many fascinating research trails. The past twenty years have been an amazingly fruitful period of research in algorithmic graph theory and structured families of graphs. Especially important have been the theory and applications of new intersection graph models such as generalizations of permutation graphs and interval graphs. These have lead to new families of perfect graphs and many algorithmic results. These are surveyed in the new Epilogue chapter in this second edition. New edition of the "Classic" book on the topic Wonderful introduction to a rich research area Leading author in the field of algorithmic graph theory Beautifully written for the new mathematician or computer scientist Comprehensive treatment
4,090 citations
28 Jun 1971
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Abstract: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.
655 citations
TL;DR: In this paper, the authors give a simple algorithm for directing all the edges of a comparability graph in such a way that the resulting graph partially orders its vertices, which they call comparability graphs.
Abstract: Let < be a non-reflexive partial ordering defined on a set P. Let G(P, <) be the undirected graph whose vertices are the elements of P, and whose edges (a, b) connect vertices for which either a < b or b < a. A graph G with vertices P for which there exists a partial ordering < such that G = G(P, <) is called a comparability graph. In §2 we state and prove a characterization of those graphs, finite or infinite, which are comparability graphs. Another proof of the same characterization has been given in (2), and a related question examined in (6). Our proof of the sufficiency of the characterization yields a very simple algorithm for directing all the edges of a comparability graph in such a way that the resulting graph partially orders its vertices.
628 citations
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Abstract: In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.
539 citations
TL;DR: It is shown that an efficient optimal algorithm for interconnecting two rows of points across an intervening channel is unlikely to exist by establishing that this problem is NP-complete.
Abstract: Interconnecting two rows of points across an intervening channel is an important problem in the design of LSI circuits. The most common methodology for producing such interconnections uses two orthogonal layers of parallel conductors and allows wires to "dogleg" arbitrarily. Although effective heuristic procedures are available for routing channels with this methodology, no efficient optimal algorithm has yet been discovered for the general case problem. We show that such an algorithm is unlikely to exist by establishing that this problem is NP-complete.
209 citations