RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model
28 Apr 2016-IEEE Transactions on Microwave Theory and Techniques (Institute of Electrical and Electronics Engineers Inc.)-Vol. 64, Iss: 6, pp 1745-1751
TL;DR: In this article, the performance of the BSIM-IMG model for fully depleted silicon-on-insulator (FDSOI) transistors is discussed with experimental data.
Abstract: In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained.
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TL;DR: This letter investigates the RF performance of a negative capacitance FinFET using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices, and finds that NC-FinFET’s cut-off frequency is a function of LaTeX, and observes that the self-heating effect in NC-finFET increases with increase ininline-formula.
Abstract: In this letter, we have investigated the RF performance of a negative capacitance FinFET (NC-FinFET) using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices. This physics-based RF model is then coupled self-consistently with the Landau-Khalatnikov equation to obtain the RF NC-FinFET model. For the first time, we report, here, the impact of ferroelectric thickness ( ${t}_{\textit {fe}}$ ) scaling on RF performance of NC-FinFET and find that NC-FinFET’s cut-off frequency ( ${f}_{\text {T}}$ ) is a function of ${t}_{\textit {fe}}$ . We also observe that the self-heating effect in NC-FinFET increases with increase in ${t}_{\textit {fe}}$ , mainly due to increase in DC current, which can be easily compensated by decreasing supply voltage. Finally, we show that NC-FinFET can achieve similar analog/RF performance as the base FinFET, even at a reduced ${V}_{\mathrm{ DD}}$ .
45 citations
TL;DR: This paper probes active terahertz circuits that have already been reported and that have the potential to be deployed in a re-engineered terAhertz radar sensor system and attempts to predict future directions in re-engineering of monolithic radar sensors.
Abstract: This paper reviews the state of emerging transistor technologies capable of terahertz amplification, as well as the state of transistor modeling as required in terahertz electronic circuit research. Commercial terahertz radar sensors of today are being built using bulky and expensive technologies such as Schottky diode detectors and lasers, as well as using some emerging detection methods. Meanwhile, a considerable amount of research effort has recently been invested in process development and modeling of transistor technologies capable of amplifying in the terahertz band. Indium phosphide (InP) transistors have been able to reach maximum oscillation frequency (fmax) values of over 1 THz for around a decade already, while silicon-germanium bipolar complementary metal-oxide semiconductor (BiCMOS) compatible heterojunction bipolar transistors have only recently crossed the fmax = 0.7 THz mark. While it seems that the InP technology could be the ultimate terahertz technology, according to the fmax and related metrics, the BiCMOS technology has the added advantage of lower cost and supporting a wider set of integrated component types. BiCMOS can thus be seen as an enabling factor for re-engineering of complete terahertz radar systems, for the first time fabricated as miniaturized monolithic integrated circuits. Rapid commercial deployment of monolithic terahertz radar chips, furthermore, depends on the accuracy of transistor modeling at these frequencies. Considerations such as fabrication and modeling of passives and antennas, as well as packaging of complete systems, are closely related to the two main contributions of this paper and are also reviewed here. Finally, this paper probes active terahertz circuits that have already been reported and that have the potential to be deployed in a re-engineered terahertz radar sensor system and attempts to predict future directions in re-engineering of monolithic radar sensors.
42 citations
Cites background from "RF Modeling of FDSOI Transistors Us..."
...The THz research gap in relation to the present [29,31,41–43] and forecast [34,35] fmax capability of transistor technologies, estimated current state of transistor modeling [44,45] and packaging [38] and reported achieved frequency operation of some THz circuits [1,42,46–52]....
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TL;DR: A compact model for the geometry and temperature dependence of Rth in FDSOI transistors is proposed and validated against experimental and Technology Computer Aided Design (TCAD) data.
18 citations
Cites methods from "RF Modeling of FDSOI Transistors Us..."
...The BSIM-IMG model [40,41] accurately captures the frequency dependent behavior of self-heating effect in FDSOI transistor as shown in Fig....
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TL;DR: In this paper, an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs is presented.
Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.
14 citations
Cites background from "RF Modeling of FDSOI Transistors Us..."
...FDSOI technology is also a preferred candidate for high frequency (HF) applications due to its high isolation and integration capabilities [9], [10]....
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TL;DR: In this paper, the authors report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors.
Abstract: In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.
13 citations
Cites background from "RF Modeling of FDSOI Transistors Us..."
...Apart from digital applications, FD-SOI transistors are also getting a strong interest from RF circuit designers for high frequency applications [10], [11]....
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References
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TL;DR: In this article, a new thermal extraction technique based on an analytically derived expression for the electro-thermal drain conductance in saturation is presented, which can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.
Abstract: Self-heating is an important issue for SOI CMOS, and hence, so is its characterization and modeling. This paper sets out how the critical parameters for modeling, i.e., thermal resistance and thermal time-constants, may be obtained using purely electrical measurements on standard MOS devices. A summary of the circuit level issues is presented, and the physical effects contributing to thermally related MOSFET behavior are discussed. A new thermal extraction technique is presented, based on an analytically derived expression for the electro-thermal drain conductance in saturation. Uniquely, standard MOSFET structures can be used, eliminating errors due to additional heat flow through special layouts. The conductance technique is tested experimentally and results are shown to be in excellent agreement with thermal resistance values obtained from noise thermometry and gate resistance measurements using identical devices. It is demonstrated that the conductance technique can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.
199 citations
"RF Modeling of FDSOI Transistors Us..." refers methods in this paper
...The model shows good agreement with experimental data in all regions of operation, which implies accurate modeling of sub-modules like mobility and current saturation....
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IBM1
TL;DR: In this article, the authors report record RF performance in 45-nm silicon-on-insulator (SOI) CMOS technology and demonstrate that RF performance scaling with channel length and layout optimization is demonstrated.
Abstract: We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fT's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fT's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.
191 citations
"RF Modeling of FDSOI Transistors Us..." refers background in this paper
...5, is smaller than the RF values of Real Y22because, at higher frequency range, dynamic self heating is removed [18]....
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TL;DR: In this article, the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage (VT) platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS) was analyzed.
Abstract: This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT ). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.
189 citations
01 Dec 2008
TL;DR: In this paper, the authors investigated the sources responsible for local and inter-die threshold voltage variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack.
Abstract: Sources responsible for local and inter-die threshold voltage (Vt) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time. Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local Vt variability and it is found that SOI thickness (TSi) variations have a negligible impact down to TSi=7 nm. Moreover, TSi scaling is shown to limit both local and inter-die Vt variability induced by gate length fluctuations. The highest matching performance ever reported for 25 nm gate length MOSFETs is achieved (AVt=0.95 mV.mum), demonstrating the effectiveness of the undoped ultra-thin FDSOI architecture in terms of Vt variability control.
173 citations
01 Dec 1998
TL;DR: In this paper, a physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance of CMOS devices.
Abstract: A physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance of CMOS devices. The accuracy of the model is validated with 2D simulations and experimental data. In addition, the effect of the gate resistance on the device noise behavior has been studied with measured data. The result shows that an accurate gate resistance model is essential for the noise modeling.
171 citations