RFID based access control protection scheme for SRAM FPGA IP cores
TL;DR: A Radio Frequency Identification (RFID) based protection scheme for Intellectual Property Protection (IPP) of Static Random Access Memory (SRAM) FPGA IP cores that overcome the limitations of existing IPP techniques is proposed.
Abstract: Field-programmable gate-array (FPGA) based hardware IP cores have emerged as an integral part of modern SOC designs. IP trading plays central role in Electronic Design Automation (EDA) industry. While the potential of IP infringement is growing fast, the global awareness of IP protection remains low. In this work, we propose a Radio Frequency Identification (RFID) based protection scheme for Intellectual Property Protection (IPP) of Static Random Access Memory (SRAM) FPGA IP cores that overcome the limitations of existing IPP techniques. Here, three types of reconfigurable RFID tags is realised in order to support the incorporation of the proposed RFID based security scheme in all the reconfigurable FPGA devices of Xilinx family. Also a special tag bypass feature is employed to increase the suitability of proposed scheme as an IPP technique for reconfigurable IP cores. The proposed scheme supports safe exchange of reconfigurable FPGA IP cores between IP providers and system developers. The results derived from the testing of hardware prototype used for the evaluation of the proposed scheme are quite encouraging and shows that the proposed security feature can be incorporated into the reconfigurable IP cores of any functionality without significant performance degradation of the reconfigurable IP cores.
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TL;DR: This paper presents a novel scheme to implement blind image watermarking based on the feature parameters extracted from a composite domain including the discrete wavelet transform (DWT), singular value decomposition (SVD), and discrete cosinetransform (DCT).
Abstract: Display Omitted A blind image watermarking scheme exploiting the DWT-SVD-DCT features is presented.The proposed PQIM reaches a trade-off between robustness and imperceptibility.Multiple watermarks can be embedded into a host image.The watermarks exhibit exceptional robustness against JPEG and JPEG2000 compression. This paper presents a novel scheme to implement blind image watermarking based on the feature parameters extracted from a composite domain including the discrete wavelet transform (DWT), singular value decomposition (SVD), and discrete cosine transform (DCT). Multiple bits can be embedded into a single image block by adjusting designated parameters via a progressive quantization index modulation technique. The quantization with respect to the feature parameters obtained in the DWT-SVD-DCT domain leads to efficient watermark extraction without referring to the original image. Experimental results show that the embedded watermarks exhibit exceptional robustness against image compression using JPEG and JPEG2000 coding standards.
58 citations
TL;DR: The purpose of this paper is to develop an enhanced radio frequency identification (RFID)-enabled graphical deduction model (rfid-GDM) for tracking the time-sensitive state, position, and other attributes of RFID-tagged objects in process flow.
Abstract: The purpose of this paper is to develop an enhanced radio frequency identification (RFID)-enabled graphical deduction model (rfid-GDM) for tracking the time-sensitive state, position, and other attributes of RFID-tagged objects in process flow. Concepts and definitions related to processes and RFID applications are first clarified, and enhanced state blocks are proposed to depict four kinds of RFID application scenarios. The implementation framework of rfid-GDM and its five steps are further addressed. Both mathematical formalization and graphical description of each step are involved. Finally, a case is studied to verify the feasibility of rfid-GDM. It is expected that rfid-GDM will provide instructions for modeling and tracking RFID-enabled process flows in diverse fields.
33 citations
Cites background from "RFID based access control protectio..."
...objects locating [16], supply chain and warehouse management [17]–[19], and access control [20]....
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TL;DR: A new protection procedure establishing an activation protocol in a similar way to the activation process in the software world is presented, named SEHAS (Secure Hardware Activation System).
Abstract: Reusable design using IP cores requires of efficient methods for protecting the Intellectual Property of the designer and the corresponding license agreements. In this work, a new protection procedure establishing an activation protocol in a similar way to the activation process in the software world is presented. The procedure, named SEHAS (Secure Hardware Activation System) allows the distribution of cores in either Blocked (not functioning) or Demo (functioning with limited features) modes, while ensuring the license agreements by identifying not only the IP core but also the implementation device, using Physically Unclonable Functions (PUF). Moreover, SEHAS secures the exchange of information between the core and the core vendor using an Elliptic Curve Cryptosystem (ECC). This secure channel allows the IP core vendor to send a unique Activation Code to the core in order to switch it to the Activated Mode, thus enabling all its features.
10 citations
TL;DR: Improved techniques based on power watermarking for introducing and extracting a digital signature from embedded cores are presented, providing a complete framework for the protection of IP cores.
Abstract: The intellectual property protection of deliverable cores is a major challenge for the design of digital systems based on reusable modules. Usually, the existing protection procedures introduce a digital signature identifying the authorship into the core under protection, which must be recovered later for verification purposes. The recovery of the signature is particularly difficult when the Intellectual Property (IP) cores are embedded into complex systems, without direct access to the input/output pins. In the present paper, improved techniques based on power watermarking for introducing and extracting a digital signature from embedded cores are presented, providing a complete framework for the protection of IP cores. Moreover, the protection module can accommodate part of the combinational logic of the core under protection, causing malfunction of the system if the protection is removed. Experimental results and several design examples show the suitability and robustness of the proposed methods.
8 citations
01 Jan 2019
TL;DR: In this chapter, the roles of RFID, social sensors, and cyber-physical system (CPS) at both inter-enterprise level and intra-Enterprise level under the context of social manufacturing are elaborated.
Abstract: In this chapter, the roles of RFID, social sensors, and cyber-physical system (CPS) at both inter-enterprise level and intra-enterprise level under the context of social manufacturing are elaborated. Advanced IoT solutions, human-machine interaction technologies and manufacturing data analysis enable humans, machines, sensors, smart workpieces and software systems to interact and cooperate with each other simultaneously for production operations. Firstly, an RFID-based graphical deduction model is constructed for tracing and monitoring material flows. Then, the concept, operational logic and implementation methods of social sensors are discussed in detail. Finally, an extended CPS framework integrating with RFID and social sensors is proposed to power social manufacturing nodes, communities, and network for production tasks. Potential application prospects of social manufacturing are also introduced from technical integration and application perspectives.
References
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TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Abstract: Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such as smartcards and ATMs. Arbiter-based physical unclonable functions (PUFs) exploit the statistical delay variation of wires and transistors across integrated circuits (ICs) in manufacturing processes to build unclonable secret keys. We fabricated arbiter-based PUFs in custom silicon and investigated the identification capability, reliability, and security of this scheme. Experimental results and theoretical studies show that a sufficient amount of inter-chip variation exists to enable each IC to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage. We show that arbiter-based PUFs are realizable and well suited to build, for example, key-cards that need to be resistant to physical attacks.
1,002 citations
Proceedings Article•
01 Jan 2008559 citations
09 Jun 2008
TL;DR: A new PUF structure called the butterfly PUF that can be used on all types of FPGAs is proposed and experimental results showing their identification and key generation capabilities are presented.
Abstract: IP protection of hardware designs is the most important requirement for many FPGA IP vendors. To this end, various solutions have been proposed by FPGA manufacturers based on the idea of bitstream encryption. An alternative solution was advocated in (E. Simpson and P. Schaumont, 2006). Simpson and Schaumont proposed a new approach based on physical unclonable functions (PUFs) for IP protection on FPGAs. PUFs are a unique class of physical systems that extract secrets from complex physical characteristics of the integrated circuits which along with the properties of unclonability provide a highly secure means of generating volatile secret keys for cryptographic operations. However, the first practical PUF on an FPGA was proposed only later in (J. Guajardo et al., 2007) based on the startup values of embedded SRAM memories which are intrinsic in some of the current FPGAs. The disadvantage of these intrinsic SRAM PUFs is that not all FPGAs support uninitialized SRAM memory. In this paper, we propose a new PUF structure called the butterfly PUF that can be used on all types of FPGAs. We also present experimental results showing their identification and key generation capabilities.
502 citations
10 Oct 2006
TL;DR: An implementation of read-proof hardware that is resistant against invasive attacks is developed and experimental evidence is given that an invasive attack on an IC equipped with this coating, reveals only a small amount of information on the key.
Abstract: In cryptography it is assumed that adversaries only have black box access to the secret keys of honest parties. In real life, however, the black box approach is not sufficient because attackers have access to many physical means that enable them to derive information on the secret keys. In order to limit the attacker’s ability to read out secret information, the concept of Algorithmic Tamper Proof (ATP) security is needed as put forth by Gennaro, Lysyanskaya, Malkin, Micali and Rabin. An essential component to achieve ATP security is read-proof hardware. In this paper, we develop an implementation of read-proof hardware that is resistant against invasive attacks. The construction is based on a hardware and a cryptographic part. The hardware consists of a protective coating that contains a lot of randomness. By performing measurements on the coating a fingerprint is derived. The cryptographic part consists of a Fuzzy Extractor that turns this fingerprint into a secure key. Hence no key is present in the non-volatile memory of the device. It is only constructed at the time when needed, and deleted afterwards. A practical implementation of the hardware and the cryptographic part is given. Finally, experimental evidence is given that an invasive attack on an IC equipped with this coating, reveals only a small amount of information on the key.
461 citations
TL;DR: This paper surveys the advanced features, design tools, and application domains for field-programmable gate arrays (FPGAs), and presents the authors' prospective view of how FPGAs will evolve to enter new application domains in the future.
Abstract: In the past two decades, advances in programmable device technologies, in both the hardware and software arenas, have been extraordinary. The original application of rapid prototyping has been complemented with a large number of new applications that take advantage of the excellent characteristics of the latest devices. High speed, very large number of components, large number of supported protocols, and the addition of ready- to-use intellectual property cores make programmable devices the preferred choice of implementation and even deployment in mass production quantities. This paper surveys the advanced features, design tools, and application domains for field-programmable gate arrays (FPGAs). The main characteristics and structure of modern FPGAs are first described to show their versatility and abundance of available design resources. Software resources are also discussed, as they are the main enablers for the efficient exploitation of the design capabilities of these devices. Current application domains are described, such as configurable computing, dynamically reconfigurable systems, rapid system prototyping, communication processors and interfaces, and signal processing. This paper also presents the authors' prospective view of how FPGAs will evolve to enter new application domains in the future.
393 citations