Robust high current ESD performance of nano-meter scale DeNMOS by source ballasting
02 May 2010-pp 853-856
TL;DR: In this paper, the impact of current crowding phenomenon and role of adding a resistor across the source and ground has been broadly addressed in a macroscopically modeled and a circuit model has been established.
Abstract: “Strong Snapback” in DeNMOS transistors leads to weak ESD performance which is often represented by low It2 and strong die to die dependence. We report here the first experimental evidence that this can be controlled with introduction of source-resistance Rs. A new microscopic model has been analyzed to understand the physics of strong snapback and explain the experimental observations. Impact of current crowding phenomenon and role of adding a resistor across the source and ground has been broadly addressed in this paper. Also the current crowding phenomenon has been macroscopically modeled and a circuit model has been established.
Citations
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Proceedings Article•
17 Oct 2011
TL;DR: In this paper, an extended source diffusion width and an island shape body contact were used to improve the ESD durability and smaller die-to-die variations of NLDMOS.
Abstract: ESD robustness dependences on the source structures of NLDMOS are studied. Improved ESD durability and smaller die-to-die variations are successfully obtained with an extended source diffusion width and an island shape body contact. Mechanisms of ESD durability improvements were analyzed by the emission microscope measurements and 3D TCAD simulations.
14 citations
Cites background from "Robust high current ESD performance..."
...The non-uniform turn-on behavior deteriorates the ESD durability and often increases die-to-die variations [7]....
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TL;DR: In this paper, the off-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic discharge (ESD) devices for high-voltage applications in standard lowvoltage complementary MOS technology is studied.
Abstract: The OFF-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an n+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both OFF-state and ESD reliability.
14 citations
Cites background from "Robust high current ESD performance..."
...source ballasting [21], and embedding an additional diffusion region that forms a parasitic silicon-controlled rectifier (SCR) structure with reversible snapback capabilities [22]....
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TL;DR: In this paper, the authors present experiments and models to understand the physics of bipolar turn-on and its impact on the onset of space-charge modulation in a drain-extended n-type metaloxide-semiconductor (DENMOS) device.
Abstract: A second-breakdown phenomenon (It2) in a drain-extended n-type metal-oxide-semiconductor (DENMOS) is associated with complex triggering of a parasitic bipolar transistor. Full comprehension of the problem requires 3-D modeling; however, there is even deficiency in the understanding of the phenomenon occurring in the 2-D cross-sectional plane. We present experiments and models to understand the physics of bipolar turn-on and its impact on the onset of space-charge modulation in a DENMOS device. We present a detailed analysis of the current paths involved during the bipolar turn-on. We show that a strong snapback is triggered due to coupling of the parasitic bipolar turn-on in a deeper region of the p-body and avalanche injection at the drain junction. Furthermore, we show that the ballast resistor formed in the drain region due to current crowding of electrons under high-current conditions can be modeled through a simplified 1-D analysis of the n+/n- resistive structure.
12 citations
TL;DR: This work builds circuit models to understand the physics of electro-thermal instability and associated thermal runway in advanced ESD protection devices under filamentation and understands the instability through appropriate modeling of localization behavior using area factor and related electro-Thermal circuit models.
19 Apr 2015
TL;DR: A new enhanced displacement-current triggering by adding floating P+ diffusions at each source finger edge for the HV LDNMOSFET is proposed, improving the HBM/ MM ESD performance improvements from 1.5kV/ 150 V to 5.5 kV/ 450 V.
Abstract: A new enhanced displacement-current triggering by adding floating P+ diffusions at each source finger edge for the HV LDNMOSFET is proposed. Unlike the conventional substrate-triggered ESD protection technologies, it is very easy to implement the scheme by the layout without any special circuit and additional component. With a total width of 1600 μm, the HBM/ MM ESD performance improvements from 1.5 kV/ 150 V to 5.5 kV/ 450 V are achieved.
Cites background from "Robust high current ESD performance..."
...As the pulse height is increased further, eventually the high level injection Kirk effect sets in [5-6]....
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References
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01 Sep 2004
TL;DR: In this article, different case studies are presented for ESD protection based on latch-up immune SCR devices, which is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices.
Abstract: There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.
76 citations
28 Sep 1999
TL;DR: In this article, the detailed physical mechanisms specific to 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) were investigated by means of TLP measurements/HBM testing, electron emission microscopy (EMMI) measurements, and 2D device simulations.
Abstract: The detailed physical mechanisms specific to 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated by means of TLP measurements/HBM testing, electron emission microscopy (EMMI) measurements, and 2D device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogenous current flow due to the unusual electrical behaviour are analyzed in single- and multifinger devices. An existing ESD-MOS compact model is extended according to the investigated phenomena. It successfully describes LDMOS high current behaviour.
42 citations
"Robust high current ESD performance..." refers background in this paper
...Vulnerability of Drain Extended NMOS under ESD events is a critical reliability issue in I/O circuits for high voltage and other mixed signal applications [1-8]....
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01 Apr 2007
TL;DR: In this article, the high current behavior of drain-extended nMOS transistors (DEnMOS) built in a state-of-the-art 65nm CMOS technology were investigated.
Abstract: In this work the high current behavior of drain-extended nMOS transistors (DEnMOS) built in a state-of-the-art 65nm CMOS technology were investigated. It shown that a sufficient level of ESD robustness (I T2~2mA/mum) can be achieved through substrate biasing. The concept will be exploited to build robust ESD protections
30 citations
TL;DR: In this paper, a modular strategy for highly flexible modeling of ESD-capable MOS compact models is introduced, which consists of the important gate-coupling effect and an approximated formulation for the avalanche multiplication factor.
13 citations
"Robust high current ESD performance..." refers background in this paper
...[8] Markus Mergens, Wolfgang Wilkening, Stephan Mettler, Heinrich Wolf and Wolfgang Fichtner "Modular approach of a high current MOS compact model for circuit-level ESD simulation including transient gatecoupling behaviour," Microelectronics Reliability, 40(1), 2000 pp....
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...Vulnerability of Drain Extended NMOS under ESD events is a critical reliability issue in I/O circuits for high voltage and other mixed signal applications [1-8]....
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TL;DR: New snapback circuit models for drain extended MOS (DEMOS) and complementary DEMOS-SCR structures used for ESD protection in high-voltage tolerant applications have been developed and it is shown that the new ESD models provide accurate representation of the structure breakdown, turn-on behaviour into conductivity modulation mode and dV/dt triggering effect, both in static and ESD transient conditions.
11 citations