Robustness of Cascode GaN HEMTs under Repetitive Overvoltage and Surge Energy Stresses
14 Jun 2021-pp 363-369
TL;DR: In this article, a 650-V rated cascode GaN high-electron-mobility-transistor (HEMT) was used for unclamped inductive switching (UIS) test.
Abstract: Surge energy robustness is essential for power semiconductor devices in many power electronics applications, such as automotive powertrains and electrical grids. Si and SiC MOSFETs can dissipate surge energy via avalanche. However, GaN high-electron-mobility-transistor (HEMT) has no avalanche capability. Recent studies have investigated the surge energy robustness of p-gate GaN HEMTs, revealing a capacitive-charging-based withstanding process. The degradation of p-gate GaN HEMT under repetitive surge energy stresses has also been reported. This work, for the first time, studies the repetitive surge energy robustness of a 650-V rated cascode GaN HEMT in the unclamped inductive switching (UIS) test. The cascode GaN HEMT shows a lower failure boundary under the repetitive UIS stress than the one under the single UIS stress. When the surge energy approaches the repetitive failure boundary, devices do not fail immediately but within limited cycles of stress. Devices were found to survive 1 million UIS cycles when the peak UIS voltage is reduced to ~80% of the failure boundary, but show considerable parametric shifts after the repetitive stress, including an on-resistance (RDS(ON)) increase during both forward and reverse conductions, a reduction in the off-state drain leakage current (I DSS ), and a negative shift of the drain-to-source capacitance (C DS ). These behaviors of device failure and degradation under repetitive UIS stresses can be explained by the buffer trapping accumulation in GaN HEMTs, which may lead to a reduction of the device dynamic breakdown voltage. This physical explanation has also been validated by physics-based TCAD simulation.
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TL;DR: In this article , the authors investigated the failure and degradation of GaN HEMTs in single-event and repetitive unclamped inductive switching (UIS) tests and provided new insights into the surge-energy and overvoltage robustness of cascode GaNHEMTs.
Abstract: Surge-energy robustness is essential for power devices in many applications such as automotive powertrains and electricity grids. While Si and SiC mosfet s can dissipate surge energy via avalanche, the GaN high-electron-mobility transistor (HEMT) has no avalanche capability and withstands surge energy by its overvoltage capability. However, a comprehensive study into the surge-energy robustness of the cascode GaN HEMT, a composite device made of a GaN HEMT and an Si mosfet , is still lacking. This article fills this gap by investigating the failure and degradation of 650-V-rated cascode GaN HEMTs in single-event and repetitive unclamped inductive switching (UIS) tests. The cascode was found to withstand surge energy by the overvoltage capability of the GaN HEMT, accompanied by avalanche in the Si mosfet . In single-event UIS tests, the cascode failed in the GaN HEMT at a peak overvoltage of 1.4–1.7 kV, which is statistically lower than the device's static breakdown voltage (1.8–2.2 kV). In repetitive UIS tests, the device failure boundary was found to be frequency dependent. At 100 kHz, the failure boundary (∼1.3 kV) is even lower than the single-event UIS boundary. After 1 million cycles of 1.25-kV UIS stresses, devices show large but recoverable parametric shifts. All these failure and degradation behaviors can be explained by the buffer trapping in the GaN HEMT and the resulted change in its dynamic breakdown voltage. Moreover, the GaN buffer trapping is believed to be assisted by the Si mosfet avalanche. An analytical model was also developed to extract the charges and losses produced in the Si avalanche in a UIS cycle. These results provide new insights into the surge-energy and overvoltage robustness of cascode GaN HEMTs.
29 citations
TL;DR: In this article , a comparative study of the parametric shift and recovery of three mainstream GaN HEMTs in repetitive overvoltage switching near their dynamic breakdown voltage (BV) was presented.
Abstract: GaN high electron mobility transistors (HEMTs) have limited avalanche capability and usually fail catastrophically in voltage overshoot up to their dynamic breakdown voltage (BV dyn ). This article presents the first comparative study of the parametric shift and recovery of three mainstream GaN HEMTs in repetitive overvoltage switching near their BV dyn . In each switching cycle, a voltage overshoot up to 90% of BV dyn was applied during the turn- off process. As the switching prolongs, all devices showed shifts in threshold voltage and saturation current, and these shifts saturated in less than 1-million cycles. These shifts are believed to be induced by the trapping of the holes generated in the impact ionization (I. I.). The device's poststress recovery was found to be dominated by the hole detrapping and through-gate removal, which highly depends on the gate stack. The gate injection transistor showed a fast natural recovery benefitted from the efficient hole removal through the Ohmic gate. The hole detrapping in the Schottky-type p-gate HEMT can be described by the Poole–Frenkel emission, allowing for the accelerated recoveries at negative gate bias and high temperatures. The hole removal in the metal-insulator-semiconductor (MIS) HEMT is blocked by the gate insulator, preventing a natural recovery. The MIS-HEMT can be recovered by applying positive gate and substrate biases, which facilitate the hole recombination in the channel. This article shows the good overvoltage robustness of all three GaN HEMTs and unveils effective methods for their poststress recovery, as well as suggests the significant impacts of I. I. and hole dynamics on the overvoltage ruggedness of GaN HEMTs near BV dyn .
10 citations
DOI•
TL;DR: In this paper , a comparative study of the parametric shift and recovery of three mainstream GaN HEMTs in repetitive overvoltage switching near their dynamic breakdown voltage (BVdyn) was presented.
Abstract: GaN high electron mobility transistors (HEMTs) have limited avalanche capability and usually fail catastrophically in voltage overshoot up to their dynamic breakdown voltage (BVdyn). This article presents the first comparative study of the parametric shift and recovery of three mainstream GaN HEMTs in repetitive overvoltage switching near their BVdyn. In each switching cycle, a voltage overshoot up to 90% of BVdyn was applied during the turn-off process. As the switching prolongs, all devices showed shifts in threshold voltage and saturation current, and these shifts saturated in less than 1-million cycles. These shifts are believed to be induced by the trapping of the holes generated in the impact ionization (I. I.). The device's poststress recovery was found to be dominated by the hole detrapping and through-gate removal, which highly depends on the gate stack. The gate injection transistor showed a fast natural recovery benefitted from the efficient hole removal through the Ohmic gate. The hole detrapping in the Schottky-type p-gate HEMT can be described by the Poole–Frenkel emission, allowing for the accelerated recoveries at negative gate bias and high temperatures. The hole removal in the metal-insulator-semiconductor (MIS) HEMT is blocked by the gate insulator, preventing a natural recovery. The MIS-HEMT can be recovered by applying positive gate and substrate biases, which facilitate the hole recombination in the channel. This article shows the good overvoltage robustness of all three GaN HEMTs and unveils effective methods for their poststress recovery, as well as suggests the significant impacts of I. I. and hole dynamics on the overvoltage ruggedness of GaN HEMTs near BVdyn.
6 citations
20 Mar 2022
TL;DR: In this paper , the authors developed a testbed for high-voltage GaN HEMTs enabling continuous overvoltage switching with a Fsw up to 1 MHz, and two types of commercial p-gate GaN high-electron-mobility transistor (HEMTs) were tested under 1 MHz overvoltages.
Abstract: Surge-energy and overvoltage ruggedness of power devices are desired in many power applications. For the GaN high-electron-mobility transistor (HEMT), a device without avalanche capability, its surge-energy and overvoltage ruggedness are both determined by its transient breakdown voltage (BV), which was recently found to be dynamic (i.e., time- and frequency-dependent). However, the switching frequency ( $F_{\text{SW}}$ ) in previous overvoltage studies is only a few kilohertz. This work, for the first time, developed a testbed for high-voltage GaN HEMTs enabling continuous overvoltage switching with a Fsw up to 1 MHz. Two types of 600/650-V commercial p-gate GaN HEMTs were tested under 1 MHz overvoltage switching. Both of them showed good ruggedness. The gate injection transistor showed a nearly $F_{\text{SW}}$ -independent dynamic BV, while the Schottky-type p-gate GaN HEMT showed a decreasing dynamic BV at higher $F_{\text{SW}}$ , e.g., 270-V lower when Fsw increases from 2 kHz to 1 MHz. These behaviors were explained by the buffer trapping/de-trapping in two types of GaN HEMTs and were validated via TCAD simulation. This work unveils the true overvoltage margin of GaN HEMTs in high-frequency converters.
5 citations
TL;DR: In this paper , a survey of avalanche and non-avalanche breakdown mechanisms in wide bandgap and ultra-wide bandgap (UWBG) power devices is presented, followed by the distinction between the static and dynamic BV.
Abstract: Breakdown voltage (BV) is arguably one of the most critical parameters for power devices. While avalanche breakdown is prevailing in silicon and silicon carbide devices, it is lacking in many wide bandgap (WBG) and ultra-wide bandgap (UWBG) devices, such as the gallium nitride high electron mobility transistor and existing UWBG devices, due to the deployment of junction-less device structures or the inherent material challenges of forming p-n junctions. This paper starts with a survey of avalanche and non-avalanche breakdown mechanisms in WBG and UWBG devices, followed by the distinction between the static and dynamic BV. Various BV characterization methods, including the static and pulse I–V sweep, unclamped and clamped inductive switching, as well as continuous overvoltage switching, are comparatively introduced. The device physics behind the time- and frequency-dependent BV as well as the enabling device structures for avalanche breakdown are also discussed. The paper concludes by identifying research gaps for understanding the breakdown of WBG and UWBG power devices.
4 citations
References
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TL;DR: In this article, the authors present self-consistent electrothermal simulations of single-finger and multifinger GaN vertical metal-oxide-semiconductor field effect transistors (MOSFETs) and lateral AlGaN/GaN high-electron-mobility transistors and compare their thermal performance.
Abstract: In this paper, we present self-consistent electrothermal simulations of single-finger and multifinger GaN vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) and lateral AlGaN/GaN high-electron-mobility transistors (HEMTs) and compare their thermal performance. The models are first validated by comparison with experimental dc characteristics, and then used to study the maximum achievable power density of the device without the peak temperature exceeding a safe operation limit of 150°C (P150°C). It is found that the vertical MOSFETs have the potential to achieve a higher P150°C than the lateral HEMTs, especially for higher breakdown voltages and higher scaling level designs.
140 citations
TL;DR: In this article, a commercial p-gate GaN high-electron-mobility transistor (HEMT) with Ohmic-and Schottky-type gate contacts is studied.
Abstract: An essential ruggedness of power devices is the capability of safely withstanding the surge energy. The surge ruggedness of the GaN high-electron-mobility transistor (HEMT), a power transistor with no or minimal avalanche capability, has not been fully understood. This article unveils the comprehensive physics associated with the surge-energy withstand process and the failure mechanisms of p-gate GaN HEMTs. Two commercial p-gate GaN HEMTs with Ohmic- and Schottky-type gate contacts are studied. Two circuits are developed to study the device surge ruggedness: an unclamped inductive switching circuit is first used to identify the withstand dynamics and failure mechanisms, and a clamped inductive switching circuit with a controllable parasitic inductance is then designed to mimic the surge energy in converter-like switching events. The p-gate GaN HEMT is found to withstand the surge energy through a resonant energy transfer between the device capacitance and the load/parasitic inductance rather than a resistive energy dissipation as occurred in the avalanche. If the device resonant voltage goes below zero, the device reversely turns on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt , or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. These results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.
81 citations
TL;DR: In this paper, the dynamic breakdown voltage (BV) and overvoltage margin of a 650-V-rated commercial GaN power HEMT in hard switching were studied. And the results suggest that the BV and over voltage margin of HEMTs in practical power switching can be significantly underestimated using the static BV.
Abstract: This work studies the dynamic breakdown voltage (BV) and overvoltage margin of a 650-V-rated commercial GaN power HEMT in hard switching. The dynamic BV measured in the hard switching circuits is over 1.4 kV, being 450 V higher than the static BV measured in the quasi-static I-V sweep. The device can survive at least 1 million hard-switching overvoltage pulses with 1.33 kV peak overvoltage (~95% dynamic BV). Recoverable device parametric shifts are observed after the 1-million pulses, featuring small reductions in threshold voltage and on-resistance. These shifts are different from the ones after the hard-switching pulses without overvoltage and are attributable to the trapping of the holes produced in impact ionization. These results suggest that the BV and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static BV.
53 citations
22 citations
01 Apr 2020
TL;DR: This work clarifies the surge-energy withstand process of a mainstream enhancement-mode GaN HEMT, the GaN gate injection transistor (GIT), and suggests the avalanche energy, a widely used JEDEC standard for the robustness of Si and SiC power MOSFETs, may not be a parameter that can directly represent the surge energy robustity of GaN high-electron-mobility-transistors.
Abstract: An essential robustness of power devices is the capability to safely withstand surge energy, which is typically characterized in an unclamped inductive switching (UIS) condition. Si and SiC power MOSFETs can dissipate surge energy through avalanching. However, GaN high-electron-mobility-transistors (HEMTs) have no or minimal avalanche capability. Prior works reported controversial interpretations of the behaviors of GaN HEMTs in UIS tests. This work, for the first time, clarifies the surge-energy withstand process of a mainstream enhancement-mode GaN HEMT, the GaN gate injection transistor (GIT). Different from Si and SiC MOSFETs, GaN GITs are shown to withstand the surge energy through a resonant energy transfer from device output capacitance back into the load inductor, followed by the device reverse conduction and inductor discharging. Almost no energy is dissipated in the device during this resonant withstand process. The failure mechanism of GaN GITs has also been identified. It was found that the surge-energy robustness of GaN GITs is almost solely determined by their transient overvoltage capability. Failure analysis and mixed-mode TCAD simulation confirm that the device failure location is consistent with the peak electric field location at the peak overvoltage transient. These results suggest the avalanche energy, a widely used JEDEC standard for the robustness of Si and SiC power MOSFETs which represents the device capability to resistively dissipate energy without thermal runaway, may not be a parameter that can directly represent the surge energy robustness of GaN HEMTs. In addition, benefited from the sub-50 ns overvoltage pulse created by the UIS test, the electrical breakdown location of hybrid-drain GIT was experimentally verified for the firs time.
18 citations