ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs

TL;DR: A routability-driven clustering method for cluster-based FPGAs that packs LUTs into logic clusters while incorporating routability metrics into a cost function and integrates the routability model into a timing-driven packing algorithm.

Abstract: Most of the FPGA's area and delay are due to routing. Considering routability at earlier steps of the CAD flow would both yield better quality and faster design process. In this paper, we discuss the metrics that affect routability in packing logic into clusters. We are presenting a routability-driven clustering method for cluster-based FPGAs. Our method packs LUTs into logic clusters while incorporating routability metrics into a cost function. Based on our routability model, the routability in timing-driven packing algorithm is analyzed. We integrate our routability model into a timing-driven packing algorithm. Our method yields up to 50% improvement in terms of the minimum number of routing tracks compared to VPack (16.5% on average). The average routing area improvement is 27% over VPack and 12% over t-VPack.

Summary

Introduction

• The organization of the paper is as follows Previous work on routability driven technology mapping and algorithms for cluster packing are discussed in Section Section describes the FPGA architecture the authors are targeting utilization and routability issues and problem formulation for the packing problem.
• The authors are introducing new metrics that are used to form a new objective function to evaluate routability.
• By clustering the logic blocks the number of connections between clusters is reduced.

RoutabilityGain B j Nets B Nets C j

• If these nets are observed closely their contributions to routability gain of the block are slightly di erent Block B has three common nets with cluster C N N and N.
• In fact the gain function originates from the third routability factor discussed in Section i e reducing pins per net.

Table Routability Gain of a Candidate Block According to a Single Net

• If the output terminal of a net is inside the cluster internal connections can be used to connect the input pins of the net located inside the cluster.
• When the net connected to a block is a multi terminal net the gain associated with the multi terminal net is computed for each block containing a terminal of the net.
• This implies a prediction of high routability gain in later stages while constructing the cluster After a highly critical connection is added to a cluster more input output connections would be added to the cluster The authors analysis in this section shows that timing and routability correlate very strongly Satisfying timing improves routability in some aspects.
• The routing results critical path delay and number of exposed nets using both packing methods t RPack and t VPack are reported in Table t RPack uses their routability gain function as described in Section.

Table Logic Size Number of Exposed Nets Number of Routing Tracks and Critical Path t

• In this paper the authors addressed routability issues and their impact on performance and routing area.
• A routability driven packing method for cluster based FPGAs is proposed.
• The authors method is able to improve the routability by decreasing the number of required tracks in the FPGA routing channels.
• This improvement was achieved by incorporating several routability factors in their packing algorithm Based on their routability model the authors analyzed the timing driven packing Criticality of a connection in terms of timing re ects the role of this connection in routability as well.

Figures

Figure Island style FPGA

Full text

UCLA
UCLA Previously Published Works
Title
Routability-driven packing: Metrics and algorithms for cluster-based FPGAs
Permalink
https://escholarship.org/uc/item/4v53n326
Journal
Journal of Circuits Systems and Computers, 13(1)
ISSN
0218-1266
Authors
Bozorgzadeh, E
Memik, S O
Yang, X
et al.
Publication Date
2004-02-01
Peer reviewed
eScholarship.org Powered by the California Digital Library
University of California

Routability-driven Packing: Metrics and Algorithms for
Cluster-based FPGAs
E. Bozorgzadeh
y
S. Ogrenci Memik
y
X. Yang
z
M. Sarrafzadeh
y
y
Computer Science Department
University of California, Los Angeles (UCLA)
3531C Bo elter Hall
Los Angeles, CA 90095, USA
e-mail:
f
elib,seda,ma jid
g
@cs.ucla.edu
z
Synplicity Inc.
600 W California Ave.
Sunnyvale, CA 94086
email: xjyang@synplicity.com
ABSTRACT
Most of an FPGA's area and delay are due to routing. Considering routability at earlier steps of the CAD ow would
both yield better quality and faster design process. In this paper, we discuss the metrics that aect routability in
packing logic into clusters. We arepresenting aroutability-driven clustering method for cluster-based FPGAs. Our
method packs LUTs into logic clusters while incorporating routability metrics into a cost function. Based on our
routability model, the routability in timing-driven packing algorithm is analyzed. We integrate our routability model
into a timing-driven packing algorithm. Our method yields up to 50
%
improvement in terms of the minimum number
of routing tracks comparedtoVPack(
16
:
5%
on average). The average routing areaimprovement is
27%
over VPack
and
12%
over t-VPack.
Keywords:
VLSI CAD, Field Programmable Gate Arrays (FPGAs), Technology mapping, Clustering Techniques,
Optimization, Algorithm.
1

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CLB
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CLB
S S
CLB
CLB
S
S
S
CLB
CLB
S
S
S
CLB
S S
CLB
S
CLB
S
Routing Segments
I/O Pad
Routing Switch Box
Configurable Logic Block
Figure 1:
Island style FPGA
1 INTRODUCTION
Today's technology allowsFPGAstobedesignedasmulti-million system gate devices at the heart of elec-
tronic systems. Since FPGA is an integral part of many digital systems, the signicance of optimization
problems in mapping circuits on FPGA has increased. There are two important issues related to the FPGA
mapping pro cess: the quality of the resulting mapping and the run-time of the to ols serving in the pro cess.
The former b eing more dominant for FPGAs, both aspects are imp ortant. Similar to ASIC design, minimiz-
ing the delayisanimportant ob jectiveaswell as minimizing the silicon area. Area of an FPGA consists of
routing area and logic area. Optimizing the utilization of b oth routing and logic resources is very crucial to
obtain a go od quality result.
FPGAs consist of smaller congurable building blo cks called logic blocks or Congurable Logic Blo cks
(CLBs), which are placed on the FPGA chip either on atwo-dimensional array (see Figure 1) or in a set
of rows. The CAD ow of mapping a circuit on FPGA consists of four ma jor stages. In the rst stage the
circuit is basically logically optimized. In stage 2, the optimized circuit is divided into CLBs of the FPGA,
which is called technology mapping. Placement and routing stages accomplish the assignment of sub circuits
on CLBs and programming the routing switches of FPGA.
Due to highly constrained and discrete interconnect structure of current FPGAs, routing is a challenging
problem. Most of the time current FPGA routers cannot use available routing resources eciently. This leads
to a large portion of the routing area to be wasted. Also, dep ending on the complexity of the particular
design routing might require a fairly large amount of time, often several hours to be completed. Hence
considering routability at earlier steps of the CAD owwould both yield a better quality of the result and
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less design time in later stages.
FPGA vendors have dierent logic block congurations. There are two kinds of CLBs: LUT-based blo cks
and multiplexor-based blocks. LUT-based logic blo cks are more popular. There have b een several contribu-
tionsindevelopment and design of FPGAs towards reducing the gap in density and performance b etween
ASIC and FPGA implementation. Hierarchical features have been added into logic and routing architecture
of FPGAs. Many commercial FPGAs, such as Xilinx, Altera, and Actel FPGAs include logic blocks that
contain several LUTs 1]. A collection of basic logic elements that are group ed together to be placed in
one complex logic blo ck is called a
cluster
(See Figure 2(a)). FPGAs with logic blocks containing multiple
basic blo cks are called
cluster-based
FPGAs. Each CLB (congurable logic block) is a cluster of basic logic
elements in cluster-based FPGAs. The structure and granularity of the logic blo ckhave a signicant impact
on the area-eciency and p erformance of the FPGA. If the logic block is ne-grained, the circuit to be im-
plemented will be distributed over more number of logic blocks. This has a negative impact on routability,
since more blo cks need to b e interconnected. Since the interconnect inside the logic blocks is hardwired, lo cal
interconnect can b e made very fast and eciently. This improves routability and decreases the load on the
router signicantly by reducing the size of problem. Two main b enets of clustering a basic blo ckinto CLBs
are sp eed in compilation and circuit delay improvement. On the other hand, it is not feasible to increase
the complexityofthelogicblocks b eyond a certain limit. If the logic blo cks b ecome to o complex it b ecomes
dicult to utilize them fully, hence several logic blo cks will b e wasted. Due to constraints on the number
of input pins and the number of blo cks within each cluster, all the resources in a cluster cannot be used
in circuit implementation. The task of assigning basic logic blo cks to clusters is called
packing
. Due to no
accurate means to estimate the interconnect at logic synthesis level, it is not easy to deal with routabilityof
circuit at logic level. However, if special properties of the interconnect available at logic level, such as sharing
among the pins, can be exploited during packing logics into basic blocks, signicant gains can be obtained
in terms of routability. In the past routability at the packing stage has not b een considered as extensively
as it has been at the technology mapping stage. Packing can bring improvements on the routability,since
after technology mapping a more accurate estimation on the interconnect is available.
In this pap er we prop ose a routability-driven packing algorithm. Weshowimprovements in routing area
upon the state-of-the-art logic packing algorithms called VPack and t-VPack: Logic Blo ckPacking Algorithm
4, 6]. We are introducing a new method to consider routabilityatthepacking stage. Our method in selecting
a block for clustering can easily b e integrated with other clustering algorithms. We are demonstrating the
eect of our method on the routabilitybysynthesizing the benchmark circuits through the complete CAD
ow. Wehavetechnology mapp ed a given circuit, then applied our routability-driven packing method for
clustering, and nally placed and routed the circuit. We present the results of the nal routing and showthat
our method improves the routability signicantly. Our new algorithm, RPack, indeed improves routability
compared to VPack. As our results on 20 largest MCNC benchmarks show in Section 5, we are able to
improve the minimum required number of routing tracks by 16.5% on an average. A preliminary version of
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this work appeared in 8]. We also integrated our routability function in timing-driven packing algorithm.
Based on our routability mo del, routabilityin timing-driven packing algorithm is analyzed. Compared to
t-VPack, the routing area is improved by 12% on an average.
The organization of the paper is as follows: Previous work on routability-driven technology mapping and
algorithms for cluster packing are discussed in Section 2. Section 3 describ es the FPGA architecture we are
targeting, utilization and routability issues and problem formulation for the packing problem. In Section 4
RPack, our routability-driven packing metho d is described. Exp erimental results are presented in Section 5.
Section 6 includes conclusions and future work.
2 Previous Work
Most commercial FPGAs use congurable blo cks containing several LUT. Packing LUTs into clusters is an
important design step intro duced for cluster-based FPGAs. It can b e viewed as a sub-task within technology
mapping stage in which logic gates are assigned to LUTs and registers. We will rst mention contributions
made in the technology mapping area. The ma jorityofresearchdevoted to technology mapping has b een
done with the ob jective of improving either timing 7, 12,18,22,13] or area-eciency 19,24,20] or trade-o
between depth and area 19]. Compared to the amount of the eort made in this area there is little work done
in the routabilitydriven technology mapping domain 15], 17]. The routability driven technology mapp er
for LUT-based arrays, Rmap 17], employs a mapping strategy that considers routability.
The packing problem is a clustering problem. Clustering has been studied extensively for various ap-
plications, such as placement 25], technology mapping 4, 17], etc. Packing is a clustering problem with
constraints on the number of input pins and the numberofLUTsineach CLB. The ob jectiveistominimize
the numb er of required CLBs to cover all the LUTs while satisfying the constraints. Betz and Rose proposed
VPackandt-VPack, logic blockpacking algorithms 4] for cluster-based FPGAs. VPack and t-VPack are
oneofthebest known packing tools for FPGAs. VPack rst packs a ip op and a LUT together into a
basic logic element using a matching based metho d. Then these BLEs are packed in a greedy manner into
logic clusters with the lo cal optimization ob jectives being to ll each cluster to its capacity and minimize the
number of used inputs to each cluster. This approach is inspired from 21]. In 6] a timing-driven packing
tool for FPGAs, t-VPack is proposed. The blocks on the critical path are preferred to b e packed together
in a CLB so that the delay can b e improved by exploiting lo cal wiring in the CLB to route the critical nets.
t-VPack delivers a better routability compared to VPack. Later, we will describ e the routability potential in
timing-driven packing algorithms. Also in 23], a packing approach is prop osed based on maximum weight
matching on circuit graph. Recently researchers in 9] have prop osed a new technique for packing logic into
clusters. Based on Rent's rule for each application, the connectivityofeach cluster is dened. In this ap-
proach routabilityisweighted according to the connectivity of the application. It is a goo d idea to consider
routability based on connectivity of the circuit. On the other hand, the weight of routability in the overall
4

Frequently asked questions

Q1. What have the authors contributed in "Routability-driven packing: metrics and algorithms for cluster-based fpgas" ?

In this paper the authors discuss the metrics that a ect routability in packing logic into clusters The authors are presenting a routability driven clustering method for cluster based FPGAs