Proceedings ArticleDOI
Route packets, not wires: on-chip interconnection networks
William J. Dally,Brian Towles +1 more
- pp 684-689
Reads0
Chats0
TLDR
This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.Abstract:
Using on-chip interconnection networks in place of ad-hoc glo-bal wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.read more
Citations
More filters
The Landscape of Parallel Computing Research: A View from Berkeley
Krste Asanovic,Ras Bodik,Bryan Catanzaro,Joseph Gebis,Parry Husbands,Kurt Keutzer,David A. Patterson,William Plishker,John Shalf,Samuel Williams,Katherine Yelick +10 more
TL;DR: The parallel landscape is frame with seven questions, and the following are recommended to explore the design space rapidly: • The overarching goal should be to make it easy to write programs that execute efficiently on highly parallel computing systems • The target should be 1000s of cores per chip, as these chips are built from processing elements that are the most efficient in MIPS (Million Instructions per Second) per watt, MIPS per area of silicon, and MIPS each development dollar.
Journal ArticleDOI
A survey of research and practices of Network-on-chip
TL;DR: The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
Proceedings ArticleDOI
A network on chip architecture and design methodology
Shashi Kumar,Axel Jantsch,Juha-Pekka Soininen,Martti Forsell,Mikael Millberg,Johnny Öberg,Kari Tiensyrjä,Ahmed Hemani +7 more
TL;DR: A packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources which is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack.
Book
Computer Architecture, Fifth Edition: A Quantitative Approach
TL;DR: The Fifth Edition of Computer Architecture focuses on this dramatic shift in the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices.
Journal ArticleDOI
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
TL;DR: This paper develops a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures and explores design trade-offs that characterize the NoC approach and obtains comparative results for a number of common NoC topologies.
References
More filters
Book
Virtual-channel flow control
TL;DR: Simulation studies show that, given a fixed amount of buffer storage per link, virtual-channel flow control increases throughput by a factor of 3.5, approaching the capacity of the network.
Book
Digital Systems Engineering
William J. Dally,John W. Poulton +1 more
TL;DR: The techniques described in this book, which were once used only in supercomputers, are now essential to the correct and efficient operation of any type of digital system.
Proceedings ArticleDOI
A delay model and speculative architecture for pipelined routers
Li-Shiuan Peh,William J. Dally +1 more
TL;DR: This paper introduces a router delay model that accurately models key aspects of modern routers and introduces a microarchitecture for a speculative virtual-channel router that significantly reduces its router latency to that of a brown hole router.
Proceedings ArticleDOI
Elastic interconnects: repeater-inserted long wiring capable of compressing and decompressing data
TL;DR: This elastic interconnect for internal communications on-chip multiprocessors is a fundamental technique capable of enhancing conventional network techniques by effectively utilizing on- chip repeater-inserted long wiring.