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Proceedings ArticleDOI

RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks

26 Jun 2015-pp 1-6
TL;DR: An intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially.
Abstract: With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH) remain dormant during the testing phase but get triggered at runtime and threaten the integrity and confidentiality of the chip. In this paper, we focus on threat to confidentiality. HTH threatens the confidentiality of such chips by leaking the secret information at runtime. We propose an intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially. Low area and low power overhead of our proposed RTNA on practical crypto SOC architectures as obtained in the experimental results confirm its practical implementation. Hardware implementation of trust generation at runtime, use of unsupervised learning and use of an intelligent architecture are the novelties of this work.
Citations
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Journal ArticleDOI
TL;DR: In this article, the authors provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture.
Abstract: The remarkable success of machine learning (ML) in a variety of research domains has inspired academic and industrial communities to explore its potential to address hardware Trojan (HT) attacks. While numerous works have been published over the past decade, few survey papers, to the best of our knowledge, have systematically reviewed the achievements and analyzed the remaining challenges in this area. To fill this gap, this article surveys ML-based approaches against HT attacks available in the literature. In particular, we first provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture. Based on the review, we further discuss the lessons learned in and challenges arising from previous studies. Despite current work focusing more on chip-layer HT problems, it is notable that novel HT threats are constantly emerging and have evolved beyond chips and to the component, device, and even behavior layers, therein compromising the security and trustworthiness of the overall hardware ecosystem. Therefore, we divide the HT threats into four layers and propose a hardware Trojan defense (HTD) reference model from the perspective of the overall hardware ecosystem, therein categorizing the security threats and requirements in each layer to provide a guideline for future research in this direction.

90 citations


Cites background or methods or result from "RTNA: Securing SOC architectures fr..."

  • ...Then, these features were input into the SNNs and learned to reveal the abnormal operations....

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  • ...BPNNs can adjust the network weights and thresholds during training to achieve a nonlinear mapping of the input and output as well as better generalization ability....

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  • ...Krishnendu et al. introduced a runtime trust neural architecture (RTNA) based on adaptive resonance theory (ART1) NNs [114]....

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  • ...Especially for wireless crypto ICs, for example, trust evaluation architecture established through on-chip ANNs [76], the incorporation of ML models can reduce the false positive rate (FPR) and false negative rate (FNR) and can effectively identify Trojans activated during operation....

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  • ...For SoC chips, for example, RNTA [114], ART1 NNs can be applied as an on-chip module to provide confidentiality protection for SoCs....

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Proceedings ArticleDOI
01 Jan 2017
TL;DR: This work proposes a self aware approach which works on the observe-decide-act (ODA) paradigm to counteract the effects of Trojans, which may induce sudden unintentional delays at runtime, affecting the basic security principles of the SoC.
Abstract: A major issue of present age system on chip (SoC) designing is meeting of stringent time to market deadlines along with the reduction of various challenges faced during design. A significant strategy adopted in tackling such a problem is to procure different components or IPs (intellectual properties) of the SoC from different third party IP vendors (3PIPs). Such a technique targets independent working of the SoC components and removes the threat of the occurrence of malicious circuitry or Hardware Trojan Horse (HTH) having a distributed architecture. However, trustworthiness of the 3PIP vendors is a concern and possibility exists in the implantation of a HTH in the individual IPs procured from them. In this work, we analyze the effects of such Trojans, which may induce sudden unintentional delays at runtime, affecting the basic security principles of the SoC. We propose a self aware approach which works on the observe-decide-act (ODA) paradigm to counteract the scenario. Existing literature on hardware security generally focus on detection of anomaly, but is silent on organizing low level security mechanisms in such a manner that the high level objective of secure task completion is facilitated at run time. Our proposed methodology not only overcomes this limitation but also ensures security without tampering the IP designs. Experimental analysis is performed using AES crypto SoC architecture. Low overhead in area and power of the security elements as obtained in experimentation supports its applicability for practical SoC applications.

17 citations


Cites background from "RTNA: Securing SOC architectures fr..."

  • ...It may affect system integrity by generating erroneous output [5], or it may affect the confidentiality of the system by leaking secret information [8]....

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  • ...A self aware approach facilitating security from confidentiality attacks at runtime is proposed in [8]....

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Book ChapterDOI
TL;DR: The results confirm that VI-based systems provide a cheap, self-sufficient, easy-to-use interface, and flexible scheme which can be easily modified to accommodate any VLSI circuit.
Abstract: Virtual instrumentation is a powerful tool that has been largely left unexplored in the domain of hardware security. It facilitates creation of automated tests to detect the presence of Trojans in a circuit thereby reducing the chance of human errors and the time required for testing. The presence of a stealthy Trojan in large VLSI circuits could lead to leakage of confidential information even in high-security applications such as defense equipment. Here, we propose the usage of virtual instrumentation to detect the presence of a delay-based Trojan in a circuit. Our results confirm that VI-based systems provide a cheap, self-sufficient, easy-to-use interface, and flexible scheme which can be easily modified to accommodate any VLSI circuit. This can also be used in other detection techniques without the need for use of complex systems.

9 citations

Journal ArticleDOI
TL;DR: This work explores how power draining ability of HTHs may reduce lifetime of the system and an offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime ofThe system.
Abstract: The present era has witnessed deployment of reconfigurable hardware or field-programmable gate arrays (FPGAs) in diverse domains like automation and avionics, which are cyber physical in nature. Such cyber physical systems are associated with strict power budgets. Efficient real-time task-scheduling strategies exist that ensure execution of maximum number of tasks within the power budget. However, these do not consider hardware threats into account. Recent literature has exposed the existence of hardware trojan horses (HTHs). HTHs are malicious circuitry that remain dormant during testing and evade detection, but get activated at runtime to jeopardize operations. HTHs can be etched into the FPGA fabric by adversaries in the untrustworthy foundries, during fabrication of the FPGAs. Even vendors selling reconfigurable intellectual properties or bitstreams that configure the FPGA fabric for task operation may insert HTHs during writing the bitstream codes. HTHs may cause a variety of attacks which may affect the basic security primitives of the system like its integrity, confidentiality or availability. In this work, we explore how power draining ability of HTHs may reduce lifetime of the system. A self-aware approach is also proposed which detects the affected resources of the system and eradicates their use in future to facilitate system reliability. An offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime of the system. Accommodating non-periodic tasks in the periodic task schedule based on available power is also focused. For experimentation, we consider tasks associated with EPFL benchmarks and demonstrate results based on the metric task success rate for periodic tasks and metric task rejection rate for non-periodic tasks.

9 citations


Cites background from "RTNA: Securing SOC architectures fr..."

  • ...Counteracting HTH attacks can be performed via several techniques, which range from offline detection [20, 21] to authentication mechanisms [22, 23] to runtime security methodologies, that may be redundancy based [16, 24] or self-aware [19, 25]....

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  • ...These can be broadly classified into redundancy based methodologies [16, 24] or self-aware approaches [19, 25, 30]....

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  • ...In prior works, use of self-aware strategy for mitigating integrity attacks [27], confidentiality attacks [17, 25] and availability attacks [18, 19] of HTHs have been explored, which ensures secure execution of real-time tasks on hardware platforms....

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Journal ArticleDOI
TL;DR: This work seeks refuge to the crypsis behavior exhibited by geckos in nature to generate a runtime security technique for SoC architectures, which can bypass runtime passive threats of a HTH.
Abstract: The rapid evolution of the embedded era has witnessed globalization for the design of SoC architectures in the semiconductor design industry. Though issues of cost and stringent marketing deadlines have been resolved in such a methodology, yet the root of hardware trust has been evicted. Malicious circuitry, a.k.a. Hardware Trojan Horse (HTH), is inserted by adversaries in the less trusted phases of design. A HTH remains dormant during testing but gets triggered at runtime to cause sudden active and passive attacks. In this work, we focus on the runtime passive threats based on the parameter delay. Nature-inspired algorithms offer an alternative to the conventional techniques for solving complex problems in the domain of computer science. However, most are optimization techniques and none is dedicated to security. We seek refuge to the crypsis behavior exhibited by geckos in nature to generate a runtime security technique for SoC architectures, which can bypass runtime passive threats of a HTH. An adaptive security intellectual property (IP) that works on the proposed security principles is designed. Embedded timing analysis is used for experimental validation. Low area and power overhead of our proposed security IP over standard benchmarks and practical crypto SoC architectures as obtained in experimental results supports its applicability for practical implementations.

8 citations


Cites methods from "RTNA: Securing SOC architectures fr..."

  • ...Nature-inspired algorithms offer an alternative to the conventional techniques for solving complex problems in the domain of computer science....

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  • ...In this strategy of This is an extended version of a previously published conference research paper [Guha et al. 2015]....

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References
More filters
Journal ArticleDOI
TL;DR: A classification of hardware Trojans and a survey of published techniques for Trojan detection are presented.
Abstract: Editor's note:Today's integrated circuits are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. This article presents a classification of hardware Trojans and a survey of published techniques for Trojan detection.

1,227 citations

Journal ArticleDOI
TL;DR: Art architectures are discussed that are neural networks that self-organize stable recognition codes in real time in response to arbitrary sequences of input patterns, which opens up the possibility of applying ART systems to more general problems of adaptively processing large abstract information sources and databases.
Abstract: The adaptive resonance theory (ART) suggests a solution to the stability-plasticity dilemma facing designers of learning systems, namely how to design a learning system that will remain plastic, or adaptive, in response to significant events and yet remain stable in response to irrelevant events. ART architectures are discussed that are neural networks that self-organize stable recognition codes in real time in response to arbitrary sequences of input patterns. Within such an ART architecture, the process of adaptive pattern recognition is a special case of the more general cognitive process of hypothesis discovery, testing, search, classification, and learning. This property opens up the possibility of applying ART systems to more general problems of adaptively processing large abstract information sources and databases. The main computational properties of these ART architectures are outlined and contrasted with those of alternative learning and recognition systems. >

1,217 citations


"RTNA: Securing SOC architectures fr..." refers background in this paper

  • ...ART [25], [26] is a neural network which facilitates autonomous learning in a complex environment....

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  • ...AES [25] is a 128 bit block non- Feistel cipher....

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  • ...DES [25] is a 64 bit block cipher consisting of 16 Feistel rounds along with a key generation module and two permutation modules....

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  • ...Adaptive Resonance Theory (ART1) neural networks [25], [26] exhibit unsupervised learning in an unknown environment....

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01 Dec 1987
TL;DR: In this article, the stability-plasticity dilemma and Adaptive Resonance Theory are discussed in the context of self-organizing learning and recognition systems, and the three R's: Recognition, Reinforcement, and Recall.
Abstract: : Partial Contents: Attention and Expectation in Self-Organizing Learning and Recognition Systems; The Stability-Plasticity Dilemma and Adaptive Resonance Theory; Competitive Learning Models; Self-Stabilized Learning by an ART Architecture in an Arbitrary Input Environment; Attentional Priming and Prediction: Matching by the 2/3 Rule; Automatic Control of Hypothesis Testing by Attentional-Orienting Interactions; Learning to Recognize an Analog World; Invariant Visual Pattern Recognition; The Three R's: Recognition, Reinforcement, and Recall; Self-Stabilization of Speech Perception and Production Codes: New Light on Motor Theory; and Psychophysiological and Neurophysiological Predictions of ART.

1,196 citations

Book
01 Jan 2015
TL;DR: This book includes the following chapters: Introduction to Modern Symmetric-Key Ciphers, Mathematics of Cryptography, and Message Integrity and Message Authentication, and Security at the Network Layer: IPSec.
Abstract: This book includes the following chapters : Introduction; Mathematics of Cryptography; Traditional Symmetric-Key Ciphers; Mathematics of Cryptography; Introduction to Modern Symmetric-Key Ciphers; Data Encryption Standard (DES); Advanced Encryption Standard (AES); Encipherment Using Modern Symmetric-Key Ciphers; Mathematics of Cryptography; Asymmetric-Key Cryptography; Message Integrity and Message Authentication; Cryptographic Hash Functions; Digital Signature; Entity Authentication; Key Management; Security at the Application Layer: PGP and S/MIME; Security at the Transport Layer: SSL and TLS; and Security at the Network Layer: IPSec.

854 citations

Journal ArticleDOI
15 Jul 2014
TL;DR: The threat of hardware Trojan attacks is analyzed; attack models, types, and scenarios are presented; different forms of protection approaches are discussed; and emerging attack modes, defenses, and future research pathways are described.
Abstract: Security of a computer system has been traditionally related to the security of the software or the information being processed. The underlying hardware used for information processing has been considered trusted. The emergence of hardware Trojan attacks violates this root of trust. These attacks, in the form of malicious modifications of electronic hardware at different stages of its life cycle, pose major security concerns in the electronics industry. An adversary can mount such an attack with an objective to cause operational failure or to leak secret information from inside a chip-e.g., the key in a cryptographic chip, during field operation. Global economic trend that encourages increased reliance on untrusted entities in the hardware design and fabrication process is rapidly enhancing the vulnerability to such attacks. In this paper, we analyze the threat of hardware Trojan attacks; present attack models, types, and scenarios; discuss different forms of protection approaches, both proactive and reactive; and describe emerging attack modes, defenses, and future research pathways.

588 citations