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Proceedings ArticleDOI

RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks

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TLDR
An intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially.
Abstract
With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH) remain dormant during the testing phase but get triggered at runtime and threaten the integrity and confidentiality of the chip. In this paper, we focus on threat to confidentiality. HTH threatens the confidentiality of such chips by leaking the secret information at runtime. We propose an intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially. Low area and low power overhead of our proposed RTNA on practical crypto SOC architectures as obtained in the experimental results confirm its practical implementation. Hardware implementation of trust generation at runtime, use of unsupervised learning and use of an intelligent architecture are the novelties of this work.

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Citations
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Journal ArticleDOI

A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

TL;DR: In this article, the authors provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture.
Proceedings ArticleDOI

Self Aware SoC Security to Counteract Delay Inducing Hardware Trojans at Runtime

TL;DR: This work proposes a self aware approach which works on the observe-decide-act (ODA) paradigm to counteract the effects of Trojans, which may induce sudden unintentional delays at runtime, affecting the basic security principles of the SoC.
Book ChapterDOI

Delay-Based Reference Free Hardware Trojan Detection Using Virtual Intelligence

TL;DR: The results confirm that VI-based systems provide a cheap, self-sufficient, easy-to-use interface, and flexible scheme which can be easily modified to accommodate any VLSI circuit.
Journal ArticleDOI

Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks

TL;DR: This work explores how power draining ability of HTHs may reduce lifetime of the system and an offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime ofThe system.
Journal ArticleDOI

Real-Time SoC Security against Passive Threats Using Crypsis Behavior of Geckos

TL;DR: This work seeks refuge to the crypsis behavior exhibited by geckos in nature to generate a runtime security technique for SoC architectures, which can bypass runtime passive threats of a HTH.
References
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Journal ArticleDOI

Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition

TL;DR: A novel framework for facilitating the acquisition of provably trustworthy hardware intellectual property (IP) that draws upon research in the field of proof-carrying code (PCC) to allow for formal yet computationally straightforward validation of security-related properties by the IP consumer.
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Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad ${I}_{\rm DDQ}$ s

TL;DR: Experimental results demonstrating the effectiveness of a Trojan detection method that is based on the analysis of a chip's Jddqs (steady-state current), which are measured simultaneously from multiple places on the chip are presented.
Journal ArticleDOI

Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream

TL;DR: This work has demonstrated the feasibility of hardware Trojan insertion in circuits mapped on FPGAs by direct modification of the FPGA configuration bitstream by a software program to insert a hardware Trojan in the design.
Journal ArticleDOI

A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions

TL;DR: This paper investigates the sensitivity of a power supply transient signal analysis method for detecting Trojans and focuses on determining the smallest detectable Trojan, i.e., the least number of gates a Trojan may have and still be detected, using a set of process simulation models that characterize a TSMC 0.18 μm process.
Journal ArticleDOI

Hardware Trojans in Wireless Cryptographic ICs

TL;DR: Challenges related to detection for Trojans designed to leak secret information through the wireless channel are investigated and statistical analysis of the side-channel signals is proposed to help detect them.
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