RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks
26 Jun 2015-pp 1-6
TL;DR: An intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially.
Abstract: With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH) remain dormant during the testing phase but get triggered at runtime and threaten the integrity and confidentiality of the chip. In this paper, we focus on threat to confidentiality. HTH threatens the confidentiality of such chips by leaking the secret information at runtime. We propose an intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially. Low area and low power overhead of our proposed RTNA on practical crypto SOC architectures as obtained in the experimental results confirm its practical implementation. Hardware implementation of trust generation at runtime, use of unsupervised learning and use of an intelligent architecture are the novelties of this work.
Citations
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TL;DR: In this article, the authors provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture.
Abstract: The remarkable success of machine learning (ML) in a variety of research domains has inspired academic and industrial communities to explore its potential to address hardware Trojan (HT) attacks. While numerous works have been published over the past decade, few survey papers, to the best of our knowledge, have systematically reviewed the achievements and analyzed the remaining challenges in this area. To fill this gap, this article surveys ML-based approaches against HT attacks available in the literature. In particular, we first provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture. Based on the review, we further discuss the lessons learned in and challenges arising from previous studies. Despite current work focusing more on chip-layer HT problems, it is notable that novel HT threats are constantly emerging and have evolved beyond chips and to the component, device, and even behavior layers, therein compromising the security and trustworthiness of the overall hardware ecosystem. Therefore, we divide the HT threats into four layers and propose a hardware Trojan defense (HTD) reference model from the perspective of the overall hardware ecosystem, therein categorizing the security threats and requirements in each layer to provide a guideline for future research in this direction.
90 citations
Cites background or methods or result from "RTNA: Securing SOC architectures fr..."
...Then, these features were input into the SNNs and learned to reveal the abnormal operations....
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...BPNNs can adjust the network weights and thresholds during training to achieve a nonlinear mapping of the input and output as well as better generalization ability....
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...Krishnendu et al. introduced a runtime trust neural architecture (RTNA) based on adaptive resonance theory (ART1) NNs [114]....
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...Especially for wireless crypto ICs, for example, trust evaluation architecture established through on-chip ANNs [76], the incorporation of ML models can reduce the false positive rate (FPR) and false negative rate (FNR) and can effectively identify Trojans activated during operation....
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...For SoC chips, for example, RNTA [114], ART1 NNs can be applied as an on-chip module to provide confidentiality protection for SoCs....
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01 Jan 2017
TL;DR: This work proposes a self aware approach which works on the observe-decide-act (ODA) paradigm to counteract the effects of Trojans, which may induce sudden unintentional delays at runtime, affecting the basic security principles of the SoC.
Abstract: A major issue of present age system on chip (SoC) designing is meeting of stringent time to market deadlines along with the reduction of various challenges faced during design. A significant strategy adopted in tackling such a problem is to procure different components or IPs (intellectual properties) of the SoC from different third party IP vendors (3PIPs). Such a technique targets independent working of the SoC components and removes the threat of the occurrence of malicious circuitry or Hardware Trojan Horse (HTH) having a distributed architecture. However, trustworthiness of the 3PIP vendors is a concern and possibility exists in the implantation of a HTH in the individual IPs procured from them. In this work, we analyze the effects of such Trojans, which may induce sudden unintentional delays at runtime, affecting the basic security principles of the SoC. We propose a self aware approach which works on the observe-decide-act (ODA) paradigm to counteract the scenario. Existing literature on hardware security generally focus on detection of anomaly, but is silent on organizing low level security mechanisms in such a manner that the high level objective of secure task completion is facilitated at run time. Our proposed methodology not only overcomes this limitation but also ensures security without tampering the IP designs. Experimental analysis is performed using AES crypto SoC architecture. Low overhead in area and power of the security elements as obtained in experimentation supports its applicability for practical SoC applications.
17 citations
Cites background from "RTNA: Securing SOC architectures fr..."
...It may affect system integrity by generating erroneous output [5], or it may affect the confidentiality of the system by leaking secret information [8]....
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...A self aware approach facilitating security from confidentiality attacks at runtime is proposed in [8]....
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TL;DR: The results confirm that VI-based systems provide a cheap, self-sufficient, easy-to-use interface, and flexible scheme which can be easily modified to accommodate any VLSI circuit.
Abstract: Virtual instrumentation is a powerful tool that has been largely left unexplored in the domain of hardware security. It facilitates creation of automated tests to detect the presence of Trojans in a circuit thereby reducing the chance of human errors and the time required for testing. The presence of a stealthy Trojan in large VLSI circuits could lead to leakage of confidential information even in high-security applications such as defense equipment. Here, we propose the usage of virtual instrumentation to detect the presence of a delay-based Trojan in a circuit. Our results confirm that VI-based systems provide a cheap, self-sufficient, easy-to-use interface, and flexible scheme which can be easily modified to accommodate any VLSI circuit. This can also be used in other detection techniques without the need for use of complex systems.
9 citations
TL;DR: This work explores how power draining ability of HTHs may reduce lifetime of the system and an offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime ofThe system.
Abstract: The present era has witnessed deployment of reconfigurable hardware or field-programmable gate arrays (FPGAs) in diverse domains like automation and avionics, which are cyber physical in nature. Such cyber physical systems are associated with strict power budgets. Efficient real-time task-scheduling strategies exist that ensure execution of maximum number of tasks within the power budget. However, these do not consider hardware threats into account. Recent literature has exposed the existence of hardware trojan horses (HTHs). HTHs are malicious circuitry that remain dormant during testing and evade detection, but get activated at runtime to jeopardize operations. HTHs can be etched into the FPGA fabric by adversaries in the untrustworthy foundries, during fabrication of the FPGAs. Even vendors selling reconfigurable intellectual properties or bitstreams that configure the FPGA fabric for task operation may insert HTHs during writing the bitstream codes. HTHs may cause a variety of attacks which may affect the basic security primitives of the system like its integrity, confidentiality or availability. In this work, we explore how power draining ability of HTHs may reduce lifetime of the system. A self-aware approach is also proposed which detects the affected resources of the system and eradicates their use in future to facilitate system reliability. An offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime of the system. Accommodating non-periodic tasks in the periodic task schedule based on available power is also focused. For experimentation, we consider tasks associated with EPFL benchmarks and demonstrate results based on the metric task success rate for periodic tasks and metric task rejection rate for non-periodic tasks.
9 citations
Cites background from "RTNA: Securing SOC architectures fr..."
...Counteracting HTH attacks can be performed via several techniques, which range from offline detection [20, 21] to authentication mechanisms [22, 23] to runtime security methodologies, that may be redundancy based [16, 24] or self-aware [19, 25]....
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...These can be broadly classified into redundancy based methodologies [16, 24] or self-aware approaches [19, 25, 30]....
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...In prior works, use of self-aware strategy for mitigating integrity attacks [27], confidentiality attacks [17, 25] and availability attacks [18, 19] of HTHs have been explored, which ensures secure execution of real-time tasks on hardware platforms....
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TL;DR: This work seeks refuge to the crypsis behavior exhibited by geckos in nature to generate a runtime security technique for SoC architectures, which can bypass runtime passive threats of a HTH.
Abstract: The rapid evolution of the embedded era has witnessed globalization for the design of SoC architectures in the semiconductor design industry. Though issues of cost and stringent marketing deadlines have been resolved in such a methodology, yet the root of hardware trust has been evicted. Malicious circuitry, a.k.a. Hardware Trojan Horse (HTH), is inserted by adversaries in the less trusted phases of design. A HTH remains dormant during testing but gets triggered at runtime to cause sudden active and passive attacks. In this work, we focus on the runtime passive threats based on the parameter delay. Nature-inspired algorithms offer an alternative to the conventional techniques for solving complex problems in the domain of computer science. However, most are optimization techniques and none is dedicated to security. We seek refuge to the crypsis behavior exhibited by geckos in nature to generate a runtime security technique for SoC architectures, which can bypass runtime passive threats of a HTH. An adaptive security intellectual property (IP) that works on the proposed security principles is designed. Embedded timing analysis is used for experimental validation. Low area and power overhead of our proposed security IP over standard benchmarks and practical crypto SoC architectures as obtained in experimental results supports its applicability for practical implementations.
8 citations
Cites methods from "RTNA: Securing SOC architectures fr..."
...Nature-inspired algorithms offer an alternative to the conventional techniques for solving complex problems in the domain of computer science....
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...In this strategy of This is an extended version of a previously published conference research paper [Guha et al. 2015]....
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References
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TL;DR: This work proposes an IP protection mechanism for FPGA designs at the level of individual IP cores, by making use of the self-reconfiguring capabilities of modern FPGAs and deploying a trusted third party to run a metering service, similar to the work of Giineysu et ah and Drimer et at
Abstract: Currently achievable intellectual property (IP) protection solutions for field-programmable gate arrays (FPGAs) are limited to single large "monolithic" configurations. However, the ever growing capabilities of FPGAs and the consequential increasing complexity of their designs ask for a modular development model, where individual IP cores from multiple parties are integrated into a larger system. To enable such a model, the availability of IP protection at the modular level is imperative. In this work, we propose an IP protection mechanism for FPGA designs at the level of individual IP cores, by making use of the self-reconfiguring capabilities of modern FPGAs and deploying a trusted third party to run a metering service, similar to the work of Giineysu et ah and Drimer et at The proposed scheme makes it possible to enforce a pay-per-use licensing scheme which holds considerable advantages, both for IP core providers as well as for system integrators. Moreover, the scheme has a minimal implementation overhead and is the first of its kind to be solely based on primitives that are already available in recent commercially available FPGA devices. This allows for an immediate and feasible deployment, in contrast to earlier proposed solutions.
69 citations
"RTNA: Securing SOC architectures fr..." refers background in this paper
...Authors in [15] propose an IP protection mechanism for FPGA designs at the modular level by a licensing scheme....
[...]
TL;DR: A hardware implementation of long- term memory and short-term memory for binary input adaptive resonance theory (ART1) neural networks is presented, based on chemical-electrical interactions in real neurons which are known to control axon release of chemical materials which in turn modulate the conductances of synapses.
Abstract: A hardware implementation of long-term memory and short-term memory for binary input adaptive resonance theory (ART1) neural networks is presented. This implementation is based on chemical-electrical interactions in real neurons which are known to control axon release of chemical materials which in turn modulate the conductances of synapses. An axon-synapse-tree structure is introduced to achieve bottom-up long-term memory. The tree is realized by voltage modulation of synapse conductances. VLSI circuits are developed to realize the different functions of ART memories. >
40 citations
"RTNA: Securing SOC architectures fr..." refers background in this paper
...Hardware implementation of an ART1 neural network is even demonstrated in [27]....
[...]
TL;DR: A low-cost solution for hardware IP protection during evaluation is proposed, by embedding a hardware Trojan inside an IP in the form of a finite state machine that effectively puts an expiry date on the usage of the IP.
Abstract: The authors propose a low-cost solution for hardware IP protection during evaluation, by embedding a hardware Trojan inside an IP in the form of a finite state machine. The Trojan disrupts the normal functional behavior of the IP on occurrence of a sequence of rare events, thereby effectively putting an expiry date on the usage of the IP.
31 citations
"RTNA: Securing SOC architectures fr..." refers background in this paper
...Hardware Trust refers to the scenario where the designed architecture prevents any illegal intrusion [14] or prevents the system from functioning maliciously [2], [18], [19]....
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25 Oct 2012
TL;DR: This paper presents the use of Benign Hardware Trojans (BHT) as a security measure for an embedded system with a software component and a hardware execution environment and demonstrates an implementation of such a BHT within a embedded system on a Xilinx Spartan-6 FPGA platform.
Abstract: In this paper we present the use of Benign Hardware Trojans (BHT) as a security measure for an embedded system with a software component and a hardware execution environment. Based on delay logic, process variation, and selective transistor aging, the BHT can be incorporated into an embedded system for the software and the hardware components to authenticate each other before functional execution. We will demonstrate an implementation of such a BHT within an embedded system on a Xilinx Spartan-6 FPGA platform. Using the same platform we will also show that the BHT security measurement has a low to modest amount of performance overhead basing on the test results from a variety of synthetic and real world benchmarks.
10 citations
"RTNA: Securing SOC architectures fr..." refers methods in this paper
...Use of a Benign Trojan as a security measure for a hardware software codesign embedded environment has been introduced in [20]....
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03 Jun 2012
TL;DR: A design for cryptographic applications that can be implemented on an FPGA taking advantage of its unique architecture and the results of the proposed error correction code are computationally efficient as compared to the conventional BCH codes.
Abstract: Field Programmable Gate Arrays (FPGAs) need built-in security not only to prevent reverse engineering, but also to prevent hacking and cloning while reconfiguring or partially reconfiguring the devices. To counter such threats, methodologies for preventing IC piracy have been developed that require a unique signature key for every fabricated chip. Physically Unclonable Functions (PUFs) can be used for such signature generation. This paper presents a design for cryptographic applications that can be implemented on an FPGA taking advantage of its unique architecture. The research is divided into three parts: The first part of the research involves development of techniques for the generation of uniquely distinguishable responses from Ring Oscillator PUFs. The second part involves development of error correction technique using Artificial Neural Networks. The third part involves a hashing function to redress the response bits. The proposed design is implemented on several Xilinx Spartan FPGAs and the Hamming distances for the responses are computed and analyzed. The uniqueness of the responses is found to be 49.0625%. It is also found that the results of the proposed error correction code are computationally efficient as compared to the conventional BCH codes.
6 citations
"RTNA: Securing SOC architectures fr..." refers methods in this paper
...Supervised learning is used in [22], [23] where usage of golden model could not be eliminated....
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...Use of supervised learning is implemented in [22], [23] but such methodologies is not free from the use of a golden model....
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