Scaling of 32nm low power SRAM with high-K metal gate
01 Dec 2008-pp 1-4
TL;DR: In this article, the authors describe SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2.
Abstract: This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG Tinv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum2 cell to meet low power application requirements.
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TL;DR: The importance of process variation in modern transistor technology is discussed, front-end variation sources are reviewed, device and circuit variation measurement techniques are presented, and recent intrinsic transistor variation performance from the literature is compared.
Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.
350 citations
TL;DR: This study proposes a 9T-SRAM cell with a data-aware-feedback-cutoff (DAFC) scheme to enlarge the write margin and dynamic-read-decoupled (DRD) schemes to prevent read-disturb for achieving deep subthreshold operation.
Abstract: SRAM suffers read-disturb and write failures at a low supply voltage, especially at deep subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback-cutoff (DAFC) scheme to enlarge the write margin and dynamic-read-decoupled (DRD) scheme to prevent read-disturb for achieving deep subthreshold operation. A 30 mV negative-pumped wordline scheme is employed to suppress bitline leakage current. The fabricated 90 nm 32 Kb 9T-SRAM macro achieves 130 mV VDDmin. All the 32 Kb 9T cells are stable across read and write operations when operated at 105 mV.
121 citations
TL;DR: It is demonstrated that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.
Abstract: We compare the performance of static random access memory (SRAM) cells based on negative capacitance (NC) FinFETs and reference FinFETs at the 7-nm technology node. We use a physics-based model for NC FinFETswhere we couple the Landau–Khalatnikovmodel of ferroelectric materials with the standard BSIM-CMG model of FinFET. For the reference FinFETs, we use the predictive model parameters optimized for SRAM design as per the ASAP7 PDK. We exploit the unique characteristics of NC-FinFETs and demonstrate that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.
74 citations
Cites background from "Scaling of 32nm low power SRAM with..."
...4(a) and 4(b) show the n-curves [28], [29] under read and write conditions respectively....
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TL;DR: This study proposes a differential data-aware power-supplied D2 AP 8T SRAM cell to address the stability and trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells.
Abstract: Due to global and local process variations, on-chip SRAM suffers failures at a low supply voltage (VDD). This study proposes a differential data-aware power-supplied D2 AP 8T SRAM cell to address the stability and trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells. Powered by its bitline pair, the proposed 8T cell applies differential data-aware-supplied voltages to its cross-coupled inverters to increase both stability margins for write and half-select accesses. A boosted bitline scheme also improves the read cell current. Two 39 Kb SRAM macros, D2 AP-8T and conventional 8T, with the same peripheral circuits were fabricated on the same testchip with 45 nm and 40 nm processes. The measured VDDmin for the D2 AP-8T macro is 240 mV-200 mV lower than that of the conventional 8T macro across lots, wafers and dies.
70 citations
08 Mar 2010
TL;DR: The efficacy of four leading write-assist techniques and their behavior at lower supply voltages in commercial SRAMs from 65nm, 45nm and 32nm low power technology nodes are reviewed.
Abstract: Read and write assist techniques are now commonly used to lower the minimum operating voltage (V min ) of an SRAM. In this paper, we review the efficacy of four leading write-assist (WA) techniques and their behavior at lower supply voltages in commercial SRAMs from 65nm, 45nm and 32nm low power technology nodes. In particular, the word-line boosting and negative bit-line WA techniques seem most promising at lower voltages. These two techniques help reduce the value of WL crit by a factor of ∼2.5X at 0.7V and also decrease the 3σ spread by ∼3.3X, thus significantly reducing the impact of process variations. These write-assist techniques also impact the dynamic read noise margin (DRNM) of half-selected cells during the write operation. The negative bit-line WA technique has virtually no impact on the DRNM but all other WA techniques degrade the DRNM by 10–15%. In conjunction with the benefit (decrease in WL crit ) and the negative impact (decrease in DRNM), overhead of implementation in terms of area and performance must be analyzed to choose the best write-assist technique for lowering the SRAM V min .
63 citations
References
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IBM1
TL;DR: In this paper, the SRAM access disturb margin (ADM) is defined as the ratio of the magnitude of the critical current to maintain SRAM stability (I/sub CRIT/) to the sigma of I/subCRIT/.
Abstract: SRAM stability during word line disturb (access disturb) is becoming a key constraint for V/sub DD/ scaling (Burnett, 1994). In this paper we present a design methodology for SRAM stability during access disturb. In this methodology, the SRAM access disturb margin (ADM) is defined as the ratio of the magnitude of the critical current to maintain SRAM stability (I/sub CRIT/) to the sigma of I/sub CRIT/. Using ADM as a figure of merit, this methodology enables one to project the cell stability margin due to process variations, e.g. V/sub T/ variation, during design of a SRAM cell. Using statistical analysis, the required stability margin for an application requirement such as array size and available redundancy can be estimated. Direct cell probing and array test can be used to verify that the stability target is met.
151 citations