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Journal ArticleDOI

Scaling theory for double-gate SOI MOSFET's

Kunihiro Suzuki1, Tetsu Tanaka1, Yoshiharu Tosaka1, Hiroshi Horie1, Yoshihiro Arimoto1 
01 Dec 1993-IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers)-Vol. 40, Iss: 12, pp 2326-2329
TL;DR: In this paper, a scaling theory for double-gate SOI MOSFETs is presented, which gives guidance for device design that maintains a sub-threshold factor for a given gate length.
Abstract: A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >
Citations
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Journal ArticleDOI
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Abstract: MOSFETs with gate length down to 17 nm are reported To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed By using boron-doped Si/sub 04/Ge/sub 06/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies

1,668 citations

Journal ArticleDOI
David J. Frank1, R.H. Dennard1, E. J. Nowak1, Paul M. Solomon1, Yuan Taur1, Hon-Sum Philip Wong1 
01 Mar 2001
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

1,417 citations


Cites background from "Scaling theory for double-gate SOI ..."

  • ...Analytically, by differentiating the Suzuki scale length [19], [52], the effect of channel thickness variation can be Fig....

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Journal ArticleDOI
07 Oct 2016-Science
TL;DR: Molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode are demonstrated, which exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106.
Abstract: Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

1,078 citations

Journal ArticleDOI
TL;DR: In this paper, the authors describe the evolution and properties of a new class of MOSFETs, called triple-plus (3 + )-gate devices, which offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOS-FET.
Abstract: In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-, triple- or quadruple-gate devices). The evolution and the properties of such devices are described and the emergence of a new class of MOSFETs, called triple-plus (3 + )-gate devices offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOSFET.

878 citations

Book
17 Oct 2007
TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.
Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

843 citations

References
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Journal ArticleDOI
R.-H. Yan1, Abbas Ourmazd1, K.F. Lee1
TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Abstract: Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

921 citations

Journal ArticleDOI
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Abstract: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device.

729 citations

Proceedings ArticleDOI
09 Dec 1990
TL;DR: In this paper, the authors describe the process fabrication and the electrical characteristics of an SOI MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it.
Abstract: Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing. The device shows evidence of volume inversion (inversion is observed not only in surface channels, but through the entire thickness of the silicon film). Because of the presence of two channels and because of reduced carrier scattering within the bulk of the silicon film, the transconductance of the 'gate-all-around' device is more than twice that of a conventional SOI device, and its subthreshold slope is nearly 60 mV/decade at room temperature. >

390 citations

Journal ArticleDOI
TL;DR: In this paper, a simple, empirical relation has been found between MOSFET parameters and the minimum channel length for which long-channel subthreshold behavior will be observed.
Abstract: As MOSFET dimensions are reduced, lower voltages, shallower junctions, thinner oxides, and heavier doping help to maintain long-channel behavior. A simple, empirical relation has been found between these parameters and the minimum channel length for which long-channel subthreshold behavior will be observed. This approximate relation provides an estimate for MOSFET parameters not requiring reduction of all dimensions by the same scale factor.

349 citations