Scheduling with dynamic voltage/speed adjustment using slack reclamation in multiprocessor real-time systems
01 Jul 2003-IEEE Transactions on Parallel and Distributed Systems (IEEE Press)-Vol. 14, Iss: 7, pp 686-700
TL;DR: This paper proposes two novel power-aware scheduling algorithms for task sets with and without precedence constraints executing on multiprocessor systems and proposes a new scheme of slack reservation to incorporate voltage/speed adjustment overhead in the scheduling algorithms.
Abstract: The high power consumption of modern processors becomes a major concern because it leads to decreased mission duration (for battery-operated systems), increased heat dissipation, and decreased reliability. While many techniques have been proposed to reduce power consumption for uniprocessor systems, there has been considerably less work on multiprocessor systems. In this paper, based on the concept of slack sharing among processors, we propose two novel power-aware scheduling algorithms for task sets with and without precedence constraints executing on multiprocessor systems. These scheduling techniques reclaim the time unused by a task to reduce the execution speed of future tasks and, thus, reduce the total energy consumption of the system. We also study the effect of discrete voltage/speed levels on the energy savings for multiprocessor systems and propose a new scheme of slack reservation to incorporate voltage/speed adjustment overhead in the scheduling algorithms. Simulation and trace-based results indicate that our algorithms achieve substantial energy savings on systems with variable voltage processors. Moreover, processors with a few discrete voltage/speed levels obtain nearly the same energy savings as processors with continuous voltage/speed, and the effect of voltage/speed adjustment overhead on the energy savings is relatively small.
Citations
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TL;DR: Two energy-conscious task consolidation heuristics are presented, which aim to maximize resource utilization and explicitly take into account both active and idle energy consumption and demonstrate their promising energy-saving capability.
Abstract: The energy consumption of under-utilized resources, particularly in a cloud environment, accounts for a substantial amount of the actual energy use. Inherently, a resource allocation strategy that takes into account resource utilization would lead to a better energy efficiency; this, in clouds, extends further with virtualization technologies in that tasks can be easily consolidated. Task consolidation is an effective method to increase resource utilization and in turn reduces energy consumption. Recent studies identified that server energy consumption scales linearly with (processor) resource utilization. This encouraging fact further highlights the significant contribution of task consolidation to the reduction in energy consumption. However, task consolidation can also lead to the freeing up of resources that can sit idling yet still drawing power. There have been some notable efforts to reduce idle power draw, typically by putting computer resources into some form of sleep/power-saving mode. In this paper, we present two energy-conscious task consolidation heuristics, which aim to maximize resource utilization and explicitly take into account both active and idle energy consumption. Our heuristics assign each task to the resource on which the energy consumption for executing the task is explicitly or implicitly minimized without the performance degradation of that task. Based on our experimental results, our heuristics demonstrate their promising energy-saving capability.
545 citations
22 Apr 2003
TL;DR: The objective is to compute the feasible partitioning that results in minimum energy consumption on multiple identical processors by using variable voltage earliest-deadline-first scheduling and develops a framework where load balancing plays a major role in producing energy-efficient partitionings.
Abstract: In this paper, we address the problem of partitioning periodic real-time tasks in a multiprocessor platform by considering both feasibility and energy-awareness perspectives: our objective is to compute the feasible partitioning that results in minimum energy consumption on multiple identical processors by using variable voltage earliest-deadline-first scheduling. We show that the problem is NP-hard in the strong sense on m /spl ges/ 2 processors even when feasibility is guaranteed a priori. Then, we develop our framework where load balancing plays a major role in producing energy-efficient partitionings. We evaluate the feasibility and energy-efficiency performances of partitioning heuristics experimentally.
329 citations
TL;DR: This work proposes a new parallel bi-objective hybrid genetic algorithm that takes into account, not only makespan, but also energy consumption, and focuses on the island parallel model and the multi-start parallel model.
327 citations
Cites background or methods from "Scheduling with dynamic voltage/spe..."
...In [29], several different scheduling algorithms using the concept of slack sharing among DVS-enabled processors were proposed....
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...The work in [29] has been extended in [30]with AND/ORmodel applications....
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...Most previous studies on scheduling with the consideration of energy consumption are conducted on homogeneous computing systems [13,29,30,10,23,4] or single-processor systems [28]....
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08 Jun 2009
TL;DR: Adagio is presented, a novel runtime system that makes DVS practical for complex, real-world scientific applications by incurring only negligible delay while achieving significant energy savings.
Abstract: Power and energy are first-order design constraints in high performance computing. Current research using dynamic voltage scaling (DVS) relies on trading increased execution time for energy savings, which is unacceptable for most high performance computing applications. We present Adagio, a novel runtime system that makes DVS practical for complex, real-world scientific applications by incurring only negligible delay while achieving significant energy savings. Adagio improves and extends previous state-of-the-art algorithms by combining the lessons learned from static energy-reducing CPU scheduling with a novel runtime mechanism for slack prediction. We present results using Adagio for two real-world programs, UMT2K and ParaDiS, along with the NAS Parallel Benchmark suite. While requiring no modification to the application source code, Adagio provides total system energy savings of 8% and 20% for UMT2K and ParaDiS, respectively, with less than 1% increase in execution time.
309 citations
Cites background from "Scheduling with dynamic voltage/spe..."
...Zhu (slack reclamation) [30] and Moncusi (hard real time end-to-end deadlines) [19] have investigated non-optimal distributed real-time energy scheduling....
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TL;DR: This work addresses the problem of scheduling precedence-constrained parallel applications on multiprocessor computer systems and presents two energy-conscious scheduling algorithms using dynamic voltage scaling (DVS) and a novel objective function and a variant from that.
Abstract: Traditionally, the primary performance goal of computer systems has focused on reducing the execution time of applications while increasing throughput. This performance goal has been mostly achieved by the development of high-density computer systems. As witnessed recently, these systems provide very powerful processing capability and capacity. They often consist of tens or hundreds of thousands of processors and other resource-hungry devices. The energy consumption of these systems has become a major concern. In this paper, we address the problem of scheduling precedence-constrained parallel applications on multiprocessor computer systems and present two energy-conscious scheduling algorithms using dynamic voltage scaling (DVS). A number of recent commodity processors are capable of DVS, which enables processors to operate at different voltage supply levels at the expense of sacrificing clock frequencies. In the context of scheduling, this multiple voltage facility implies that there is a trade-off between the quality of schedules and energy consumption. To effectively balance these two performance goals, we have devised a novel objective function and a variant from that. The main difference between the two algorithms is in their measurement of energy consumption. The extensive comparative evaluations conducted as part of this work show that the performance of our algorithms is very compelling in terms of both application completion time and energy consumption.
306 citations
Cites background from "Scheduling with dynamic voltage/spe..."
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...The extensive comparative evaluations conducted as part of this work show that the performance of our algorithms is very compelling in terms of both application completion time and energy consumption....
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References
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TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Abstract: Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >
2,690 citations
Journal Article•
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Abstract: Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations This optimum is achieved by trading increased silicon area for reduced power consumption >
2,337 citations
"Scheduling with dynamic voltage/spe..." refers background in this paper
...utilized functional units [4], [7]....
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...Processor speed is almost linearly related to the supply voltage: S 1⁄4 k ðVddÿVtÞ 2 Vdd , where k is constant and Vt is the threshold voltage [4], [7]....
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PARC1
TL;DR: This paper proposes a simple model of job scheduling aimed at capturing some key aspects of energy minimization, and gives an off-line algorithm that computes, for any set of jobs, a minimum-energy schedule.
Abstract: The energy usage of computer systems is becoming an important consideration, especially for battery-operated systems. Various methods for reducing energy consumption have been investigated, both at the circuit level and at the operating systems level. In this paper, we propose a simple model of job scheduling aimed at capturing some key aspects of energy minimization. In this model, each job is to be executed between its arrival time and deadline by a single processor with variable speed, under the assumption that energy usage per unit time, P, is a convex function, of the processor speed s. We give an off-line algorithm that computes, for any set of jobs, a minimum-energy schedule. We then consider some on-line algorithms and their competitive performance for the power function P(s)=s/sup p/ where p/spl ges/2. It is shown that one natural heuristic, called the Average Rate heuristic, uses at most a constant times the minimum energy required. The analysis involves bounding the largest eigenvalue in matrices of a special type.
1,525 citations
"Scheduling with dynamic voltage/spe..." refers background or methods in this paper
...Using this feature, several software techniques have been proposed to adjust the supply voltage, especially for mobile or uniprocessor systems [1, 2, 6, 14, 17, 18, 20, 26]....
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...describe an optimal preemptive scheduling algorithm for independent tasks running with variable speed [26]....
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21 Oct 2001
TL;DR: This paper presents a class of novel algorithms that modify the OS's real-time scheduler and task management service to provide significant energy savings while maintaining real- time deadline guarantees, and shows that these RT-DVS algorithms closely approach the theoretical lower bound on energy consumption.
Abstract: In recent years, there has been a rapid and wide spread of non-traditional computing platforms, especially mobile and portable computing devices. As applications become increasingly sophisticated and processing power increases, the most serious limitation on these devices is the available battery life. Dynamic Voltage Scaling (DVS) has been a key technique in exploiting the hardware characteristics of processors to reduce energy dissipation by lowering the supply voltage and operating frequency. The DVS algorithms are shown to be able to make dramatic energy savings while providing the necessary peak computation power in general-purpose systems. However, for a large class of applications in embedded real-time systems like cellular phones and camcorders, the variable operating frequency interferes with their deadline guarantee mechanisms, and DVS in this context, despite its growing importance, is largely overlooked/under-developed. To provide real-time guarantees, DVS must consider deadlines and periodicity of real-time tasks, requiring integration with the real-time scheduler. In this paper, we present a class of novel algorithms called real-time DVS (RT-DVS) that modify the OS's real-time scheduler and task management service to provide significant energy savings while maintaining real-time deadline guarantees. We show through simulations and a working prototype implementation that these RT-DVS algorithms closely approach the theoretical lower bound on energy consumption, and can easily reduce energy consumption 20% to 40% in an embedded real-time system.
1,265 citations
"Scheduling with dynamic voltage/spe..." refers background in this paper
...Hence, Ca 50 percent and Ka 0. Similarly, the AMD K6-2+ was measured to have an overhead of 0.4 ms to change voltage and 40 st o change frequency [ 22 ]....
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07 Feb 2000
TL;DR: In this article, the authors proposed a dynamic voltage scaling (DVS) strategy to achieve the highest possible energy efficiency for time-varying computational loads, which can reduce energy consumption for low computational periods while retaining peak performance when required.
Abstract: The microprocessor system in portable electronic devices often has a time-varying computational load which is comprised of: (1) compute-intensive and low-latency processes, (2) background and high-latency processes, and (3) system idle. The key design objectives for the processor systems in these applications are providing the highest possible peak performance for the compute-intensive code (e.g., handwriting recognition, image decompression) while maximizing the battery life for the remaining low performance periods. If clock frequency and supply voltage are dynamically varied in response to computational load demands, then energy consumed per process can be reduced for the low computational periods, while retaining peak performance when required. This strategy, which achieves the highest possible energy efficiency for time-varying computational loads, is called dynamic voltage scaling (DVS).
1,009 citations
"Scheduling with dynamic voltage/spe..." refers methods in this paper
...Thus, for AMD, Ca 4 percent and Ka 0. For the lpARM processor that needs 70 s to change voltage [ 5 ], Ca 0:7 percent and Ka 0....
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