Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting
11 Jun 2020-IEEE Transactions on Very Large Scale Integration Systems (IEEE)-Vol. 28, Iss: 9, pp 1979-1992
TL;DR: A novel methodology to secure hardware accelerators against ownership threats/IP piracy using biometric fingerprinting, followed by embedding fingerprint’s digital template into the design in the form of secret biometric constraints; thereby generating a secured hardware accelerator design.
Abstract: This article presents a novel methodology to secure hardware accelerators (such as digital signal processing (DSP) and multimedia intellectual property (IP) cores) against ownership threats/IP piracy using biometric fingerprinting. In this approach, an IP vendor’s biometric fingerprint is first converted into a corresponding digital template, followed by embedding fingerprint’s digital template into the design in the form of secret biometric constraints; thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of 11 different fingerprints on probability of coincidence (Pc) metric. As evident, the proposed approach achieves a very low Pc value in the range of 2.22E−3 to 4.35E−6. Further, the biometric fingerprint achieves total constraints size between minimum 350 bits to maximum 895 bits; 2) impact of six different resource constraints on the design cost overhead of JPEG compression hardware postembedding biometric fingerprint. As evident, for all the resource constraints implemented, the design cost overhead is 0%; and 3) comparative analysis of proposed biometric fingerprint with recent work, for five different signature strength values, in terms of Pc. As evident, the proposed approach achieves minimum 3.9E+2 times and maximum 6.9E+4 times lower Pc, when compared to recent work.
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TL;DR: Wang et al. as mentioned in this paper used a lightweight convolutional model in the backbone network and employed a triplet loss function to train the model, which not only improves the matching accuracy, but also satisfies the real-time matching requirements.
Abstract: Even though the deep neural networks have strong feature representation capability and high recognition accuracy in finger vein recognition, the deep models are computationally intensive and poor in timeliness. To address these issues, this article proposes a lightweight algorithm for finger vein image recognition and matching. The proposed algorithm uses a lightweight convolutional model in the backbone network and employs a triplet loss function to train the model, which not only improves the matching accuracy, but also satisfies the real-time matching requirements. In addition, the Mini-region of interest (RoI) and finger vein pattern feature extraction also effectively solve the problems of large amounts of calculation and background noise. Moreover, the present model recognizes new categories based on the feature vector space constructed by the finger vein recognition system, so that new categories can be recognized without retraining the model. The results show that the finger vein recognition and matching algorithm proposed in this article achieves 99.3% and 99.6% in recognition accuracy and 14.2 and 16.5 ms in matching time for the dataset Shandong University Machine Learning and Applications Laboratory-Homologous Multimodal Biometric Traits (SDUMLA-HMT) and Peking University Finger Vein Dataset (PKU-FVD), respectively. These metrics show that our approach is time-saving and more effective than previous algorithms. Compared with the state-of-the-art finger vein recognition algorithm, the proposed algorithm improves 1.45% in recognition accuracy while saving 45.7% in recognition time.
25 citations
TL;DR: In this article, a new method is proposed to verify air signatures by analyzing finger movements and cerebral activities together with the help of sensors in next-generation consumer electronic (CE) devices.
Abstract: Rapid advancement in sensor technology through miniaturization of electronic components has enabled the consumer electronic (CE) research community including the manufacturers to embed various utility sensors into handheld devices. In addition to traditional sensors such as Inertial Measurement Unit (IMU), camera, fingerprint or proximity, futuristic sensors such as Electroencephalogram (EEG) or Electromyography (EMG) are also being included in the next-generation CE devices. Air or touch signature-based authentication systems are common in modern CE devices. However, cerebral activities clubbed with gestures will certainly enhance the security of such authentication systems. This can help consumers from being the victims of shoulder surfing attacks. In this article, a new method is proposed to verify air signatures by analyzing finger movements and cerebral activities together with the help of sensors in next-generation CE devices. Signatures are first spotted by analyzing 3D geometrical features of the finger movement during the signing. Concurrent EEG responses are then analyzed for the verification. Hidden Markov Model (HMM) and Random Forest (RF) classifiers have been used to train the system. Experiments reveal that EEG signals are highly correlated with the finger movements during air signatures even in the presence of motion artifacts. Therefore, false-positive rates have significantly reduced as compared to the existing tracking-based methods. Verification accuracy as high as 95.5% (HMM) and 98.5% (RF) have been recorded when tested on our dataset.
6 citations
TL;DR: A novel facial biometrics-based hardware security methodology to secure hardware accelerators against ownership threats/IP piracy by embedding facial signature's digital template into the design in the form of secret biometric constraints, thereby generating a secured hardware accelerator design.
Abstract: This article presents a novel facial biometrics-based hardware security methodology to secure hardware accelerators [such as digital signal processing (DSP) and multimedia intellectual property (IP) cores] against ownership threats/IP piracy. In this approach, an IP vendor’s facial biometrics is first converted into a corresponding facial signature representing digital template, followed by embedding facial signature’s digital template into the design in the form of secret biometric constraints, thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of five different facial biometrics constraints on probability of coincidence (Pc) metric (indicating strength of digital evidence). The proposed approach achieves a very low Pc value in the range of 1.54E–5 to 2.01E–5; 2) impact of different facial feature set of a facial biometric image on total number of generated secret constraints and Pc. As evident, for all facial feature sets implemented, Pc ranges between 3.31E–4 and 2.01E–5; and 3) comparative analysis of proposed approach with recent work, for different DSP applications and five different facial biometric images, in terms of Pc. As evident, the proposed approach achieves significantly lower Pc, compared with recent work.
6 citations
Cites background or methods from "Securing Hardware Accelerators for ..."
...COMPARISON OF PC WITH RESPECT TO RELATED WORK [4]...
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...DESIGN COST COMPARISON OF THE PROPOSED FACIAL BIOMETRIC APPROACH WITH FINGERPRINT BIOMETRIC APPROACH [4] AND BASELINE...
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...In addition, a fraud IP user may dishonestly claim the IP ownership [4]....
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...In addition, Table VII compares the “Pc” of proposed approach with fingerprint biometric-based hardware security approach [4]....
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...3029245 synthesized into hardware using high-level synthesis (HLS) phase of VLSI design process [4]....
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TL;DR: The results confirm that the proposed hardware accelerators achieve strong security and low design cost.
Abstract: Hardware accelerators are widely used as computationally-intensive cores in consumer electronics (CE) applications. However security and speed of such hardware accelerators, that are responsible for computing data-intensive tasks, play an important role in improving consumer experience in terms of safety and performance. This article presents novel low power multi-modal hardware accelerator architectures viz. application specific processor and functionally reconfigurable processor for image processing filter of $3\times 3$ kernel matrix size. In the proposed functionally reconfigurable processor of $3\times 3$ filter, the same design can be used for five different image processing filters - blurring, sharpening, vertical embossment, horizontal embossment and Laplace edge detection, by varying control input. Further, application specific processor designs of these five types of $3\times 3$ filters are also presented in this article. Additionally, application specific processor architecture of $5\times 5$ filter kernel matrix size is also reported in this article. The results confirm that the proposed hardware accelerators achieve strong security and low design cost.
4 citations
Cites background from "Securing Hardware Accelerators for ..."
...Additionally, security of hardware accelerators [5], [6] used in CE systems is also relevant, especially from the perspective of end consumer safety, due to possible secret Trojan insertions (malicious logic) that poses threat to safety and reliability....
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TL;DR: In this paper, a novel contactless palmprint biometric hardware security approach for securing DSP-based coprocessors is presented, which is capable of generating secret biometric palmprint constraints that are embedded in DSP designs used in consumer electronics systems to detect counterfeited versions.
Abstract: This paper presents a novel contact-less palmprint biometric hardware security approach for securing DSP based coprocessors. The proposed approach is capable of generating secret biometric palmprint constraints that are embedded in DSP designs used in consumer electronics systems to detect counterfeited versions. Any DSP based intellectual property (IP) core can be embedded with proposed palmprint signature to distinguish between authentic and its fake versions. In the proposed approach, the authentic biometric palmprint is first converted into its equivalent palmprint signature representing digital template based on palmprint feature set, followed by embedding palmprint signature’s digital template into the design in the form of secret biometric constraints. The biometric palmprint constraints generated through the proposed approach is non-replicable and non-vulnerable compared to other signature based scheme such as hardware steganography and hardware watermarking. The proposed approach exploits several security features such as: palmprint nodal points, palmprint features, palmprint feature ordering, concatenation mechanism of features etc to generate a robust palmprint hardware security constraint. The results of the proposed approach indicated stronger probability of co-incidence and stronger tamper tolerance ability than recent related works.
2 citations
References
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TL;DR: Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.
Abstract: Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.
468 citations
"Securing Hardware Accelerators for ..." refers background in this paper
...which compose of various multivendor third-party intellectual property (3PIP) cores [1]....
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TL;DR: A new security metric and a method to deliver strong logic locking are introduced and it is demonstrated that an attacker can decipher the locked netlist, in a time linear to the number of keys, by sensitizing the key-bits to the output.
Abstract: Due to globalization of integrated circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware Trojans. EPIC locks the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the locked netlist, in a time linear to the number of keys, by sensitizing the key-bits to the output. We then develop techniques to fix this vulnerability and make an attacker’s effort truly exponential in the number of inserted keys. We introduce a new security metric and a method to deliver strong logic locking.
287 citations
TL;DR: This work introduces a multiplexor-based locking strategy that preserves test response allowing IC testing by an untrusted party before activation, and demonstrates a simple yet effective attack against a locked circuit that does not preserve test response.
Abstract: The increasing IC manufacturing cost encourages a business model where design houses outsource IC fabrication to remote foundries. Despite cost savings, this model exposes design houses to IC piracy as remote foundries can manufacture in excess to sell on the black market. Recent efforts in digital hardware security aim to thwart piracy by using XOR-based chip locking, cryptography, and active metering. To counter direct attacks and lower the exposure of unlocked circuits to the foundry, we introduce a multiplexor-based locking strategy that preserves test response allowing IC testing by an untrusted party before activation. We demonstrate a simple yet effective attack against a locked circuit that does not preserve test response, and validate the effectiveness of our locking strategy on IWLS 2005 benchmarks.
152 citations
TL;DR: This paper first uses several preprocessing steps on the binary image in order to eliminate the spurious lakes and dots, and to reduce the spurious islands, bridges, and spurs in the skeleton image to extract fingerprint minutiae.
Abstract: In this paper, we propose to use the fingerprint valley instead of ridge for the binarization-thinning process to extract fingerprint minutiae. We first use several preprocessing steps on the binary image in order to eliminate the spurious lakes and dots, and to reduce the spurious islands, bridges, and spurs in the skeleton image. By removing all the bug pixels introduced at the thinning stage, our algorithm can detect a maximum number of minutiae from the fingerprint skeleton using the Rutovitz Crossing Number. This allows the true minutiae preserved and false minutiae removed in later postprocessing stages. Finally, using the intrinsic duality property of fingerprint image we develop several postprocessing techniques to efficiently remove spurious minutiae. Especially, we define an H-point structure to remove several types of spurious minutiae including bridge, triangle, ladder, and wrinkle all together. Experimental results clearly demonstrate the effectiveness of the new algorithms.
143 citations
Additional excerpts
...pixel P , the CN is defined as follows [21]:...
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TL;DR: The essence of the new approach is the addition of a set of design and timing constraints which encodes the author's signature which results in signature data that is highly resilient, difficult to detect and remove, and yet is easy to verify and can be embedded in designs with very low hardware overhead.
Abstract: We introduce dynamic watermarking techniques for protecting the value of intellectual property of CAD and compilation tools and reusable design components. The essence of the new approach is the addition of a set of design and timing constraints which encodes the author's signature. The constraints are selected in such a way that they result in a minimal hardware overhead while embedding a unique signature that is difficult to remove and forge. Techniques are applicable in conjunction with an arbitrary behavioral synthesis task such as scheduling, assignment, allocation, transformation, and template matching.On a large set of design examples, studies indicate the effectiveness of the new approach that results in signature data that is highly resilient, difficult to detect and remove, and yet is easy to verify and can be embedded in designs with very low hardware overhead. For example, the probability that the same design with the embedded signature is obtained by any other designers by themselves is less than 1 in 10102, and no register overhead was incurred. The probability of tampering, the probability that part of the embedded signature can be removed by random attempts, is shown to be extremely low, and the watermark is additionally protected from such tampering with error-correcting codes.
137 citations