Selecting built-in self-test configurations for field programmable gate arrays
16 Sep 1996-pp 29-35
TL;DR: The memory requirements as well as the testing time are minimized by selecting a few BIST configurations which provide high fault coverage for inspection tests at board and system manufacturing aswell as for efficient system diagnostics and field testing.
Abstract: In our previous work, we have described a built-in self-test (BIST) approach for RAM-based field programmable gate arrays (FPGAs), which exploits the reprogrammability of the FPGA to create BIST logic only during off-line testing. The cost is additional external memory required to store the BIST reconfiguration data, leaving all FPGA logic resources available for system functions. In this paper, the memory requirements as well as the testing time are minimized by selecting a few BIST configurations which provide high fault coverage for inspection tests at board and system manufacturing as well as for efficient system diagnostics and field testing.
Citations
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20 Oct 1996
TL;DR: In this paper, an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays.
Abstract: We present an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays. The new architecture is easily scalable with increasing size of FPGAs and ensures routability of the various configurations required to completely test the FPGA in three test sessions. In addition, the BIST approach addresses RAM mode testing as well as testing the adder/subtractor modes in FPGAs.
72 citations
TL;DR: A novel approach to testing lookup table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper, and a novel built-in self-test structure is also proposed.
Abstract: A novel approach to testing lookup table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs of an LUT. The whole chip is configured as a group of one-dimensional iterative logic arrays of cells. We assume that in each linear cell array, there is at most one faulty cell, and that multiple faulty CLBs in the same cell can be detected. For the LUT, a fault may occur at the memory matrix, decoder, input or output lines. The switch stuck-on and stuck-off fault models are adopted for multiplexers. New conditions for C-testability of programmable reconfigurable arrays are also derived. Our idea is to configure the cells so as to make each cell function bijective. This property is helpful for applying pseudoexhaustive test patterns to each cell and propagating errors to the observable outputs. In order to detect all the faults defined, k+2 configurations are required, and the resulting number of test patterns is 2(superscript k). A novel built-in self-test structure is also proposed in this paper. The input patterns can be easily generated with a k-bit counter. The number of configurations for our BIST structures is 2k+4. Our BIST approaches also have the advantage of requiring fewer hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, three test sessions are required. However, the maximum number of configurations for diagnosing a faulty CLB is k+4.
32 citations
Cites methods from "Selecting built-in self-test config..."
...Here, we will focus on the testing of unprogrmmed FPGAs, on which many research results have been published [4-19]....
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Patent•
01 Jul 2003TL;DR: In this paper, the authors present a system for delay-fault testing field programmable gate arrays (FPGA's), applicable both for off-line manufacturing and system-level testing, as well as for on-line testing within the framework of the roving self-test area (STARs) approach.
Abstract: Systems and methods for delay-fault testing field programmable gate arrays (FPGA's), applicable both for off-line manufacturing and system-level testing, as well as for on-line testing within the framework of the roving self-test area (STARs) approach are described. In one method according to the present invention, two or more paths under test receive a test pattern approximately simultaneously. The two paths are substantially identical and thus should propagate the signal in approximately the same amount of time. An output response analyzer receives the signal from each of the paths and determines the interval between them. The output response analyzer next determines whether a delay fault has occurred based at least in part on the interval. In one embodiment, the output response analyzer comprises an oscillator and a counter. The oscillator generates an oscillating signal during the interval between the test signal propagates through the first path under test and when the test signal propagates through the last path under test.
30 citations
TL;DR: A novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs) configured to implement a bijective function to simplify the testing of the whole cell array and a novel built-in self-test structure is proposed.
Abstract: In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.
10 citations
24 Oct 2001
TL;DR: A novel built-in self-test (BIST) scheme for configurable logic blocks (CLBs) of Xilinx XC4000 field programmable gate arrays (FPGAs) and the test of the dedicated carry logic module (CLM) within a CLB is included for the first time.
Abstract: This paper presents a novel built-in self-test (BIST) scheme for configurable logic blocks (CLBs) of Xilinx XC4000 field programmable gate arrays (FPGAs). The test of the dedicated carry logic module (CLM) within a CLB is included for the first time. A minimum of eight CLB test configurations is given. A centralized BIST architecture supports the single stuck-at fault test of the CLM and the whole CLB. The scheme is also capable of locating any faulty CLBs with the maximum diagnostic resolution, two adjacent CLBs.
9 citations
Cites background or methods from "Selecting built-in self-test config..."
...Separate treatments have been used to achieve satisfactory test coverage [2-12]....
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...Device level testing requires full I/O access during a test [2-4, 9-12], whereas built-in selftest (BIST) includes a BIST circuit in a TC and requires a small number of I/O pins [5-8]....
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...the download time) is much longer than the test application time for CLBs, therefore, minimization of CLB TCs is of great importance [6, 8, 9, 11]....
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...Considerable efforts have been made in developing testing strategies for CLBs [2-12]....
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References
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Book•
01 Sep 1998TL;DR: Memory modeling functional testing: reduced functional RAM chip model Functional RAM chip testing functional ROM chip testingfunctional memory array testing functional memory board testing electrical testing: parametric testing dynamic testing on chip testing conclusions: address line scrambling various proofs software package.
Abstract: Memory modeling functional testing: reduced functional RAM chip model functional RAM chip testing functional ROM chip testing functional memory array testing functional memory board testing electrical testing: parametric testing dynamic testing on chip testing conclusions: address line scrambling various proofs software package.
883 citations
TL;DR: A new approach to test pattern generation which is particularly suitable for self-test is described, which requires much less computation time and fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected.
Abstract: A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault simulation or fault modeling is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected. The test patterns are easily generated algorithmically either by program or hardware.
229 citations
"Selecting built-in self-test config..." refers background or methods in this paper
...This results in maximal fault coverage without explicit fault model assumptions and without fault simulation [ 3 ]....
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...Our testing strategy relies on pseudoexhaustive testing, which results in maximal fault coverage without explicit fault model assumptions and without fault simulation [ 3 ]....
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28 Apr 1996
TL;DR: A new approach for Field Programmable Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, achieving BIST without any area overhead or performance penalties to the system function implemented by the FPGA.
Abstract: We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcome these limitations.
167 citations
"Selecting built-in self-test config..." refers background or methods in this paper
...We recently proposed a BlST approach for FPGA testing that exploits the reprogrammability of an FPGA to create the BlST logic by configuring it only during the offline testing process [1][ 2 ]....
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...The original gate level model used in [ 2 ] was modified in order to more accurately reflect the actual implementation of the PLB....
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...At the other extreme, comprehensive tests require many more configurations (18 in [ 2 ] and 21 in [5])....
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...30 their various modes of operation [1][ 2 ]....
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...The original nine BlST configurations in [ 2 ] were also slightly modified and are summarized on Table 2 (note that the 5-variable and 5xvariable modes for the LUT reflect the two programmable options for the 5-variable mode of operation)....
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28 Apr 1996
TL;DR: This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics by introducing a hybrid fault model based on a physical and behavioral characterization.
Abstract: This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics. A hybrid fault model is introduced based on a physical and behavioral characterization; this permits the detection of a single fault, as either a stuck-at or a functional fault. A general approach which regards testing as can application for the reconfigurable FPGA, is then proposed. It is shown that different arrangements of disjoint one-dimensional arrays with unilateral horizontal connections and common vertical input lines provide a very good solution. A further feature that is considered for array testing, is the relation between the configuration of the logic blocks and the number of I/O pins in the chip. As an example, the proposed approach is applied for testing the Xilinz 4000 family of FPGAs.
106 citations
TL;DR: Two algorithms are proposed for self-testing of embedded bedded RAMs, both of which can detect a large variety of stuck-at and non-stuck-at faults.
Abstract: The authors present a built-in self-test (BIST) method for testing embedded memories. Two algorithms are proposed for self-testing of embedded bedded RAMs, both of which can detect a large variety of stuck-at and non-stuck-at faults. The hardware implementation of the methods requires a hardware test-pattern generator, which produces address, data, and read/write inputs. The output responses of the memory can be compressed by using a parallel input signature analyzer, or they can be compared with expected responses by an output comparator. The layout of memories has been considered in the design of additional BIST circuitry. The authors conclude by evaluating the two schemes on the basis of area overhead, performance degradation, fault coverage, test application time, and testing of self-test circuitry. The BIST overhead is very low and test time is quite short. Six devices, with one of the test schemes, have been manufactured and are in the field.
96 citations