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Book ChapterDOI

Self-repairing Functional Unit Design in an Embedded Out-of-Order Processor Core

01 Jan 2019-pp 365-374
TL;DR: The proposed solution maximizes the reliability of the processor core without much area and time overhead and utilizes the existing reconfigurable hardware in the new range of embedded systems like Intel Atom E6 × 5C series.
Abstract: With increasing complexity of processor architectures and their vulnerability to hard faults, it is vital to have self-repairing processor architectures. This paper proposes the idea of autonomic repairing of permanent hard faults in the functional units of an out-of-order processor core using reconfigurable FPGA. The technique proposed utilizes the existing reconfigurable hardware in the new range of embedded systems like Intel Atom E6 × 5C series. The proposed technique includes an on-chip buffer, a fault status table (fully associative) and few control signals to the existing core. To perform self-repairing, decoder will identify reference to the faulty unit and initiate the reconfigurable hardware to be configured as the faulty unit referenced. Dispatch unit will help resolve the reservation station conflicts for the reconfigurable hardware. Execution of instruction that referenced the faulty unit gets executed in the reconfigurable unit. Dispatch unit and the buffers helps complete the out-of-order execution and in-order commit of the instructions that referenced a faulty unit. A hypothetical architecture that loosely resembles ALPHA 21264 is designed as a test bed for analyzing the proposed self-repairing mechanism. Area and time overhead analysis are done using Cadence NCVerilog simulator, Xilinx-Vivado ISE and FPGA Prototype board. Spatial and temporal costs of the proposed design are around 2% and 2.64% respectively. With recent increase in hybrid architectures that has FPGA tightly coupled with ASIC processor core, the proposed solution maximizes the reliability of the processor core without much area and time overhead.
References
More filters
Proceedings ArticleDOI
10 Nov 2002
TL;DR: A new hybrid ASIC/FPGA chip architecture that is being developed in collaboration between IBM and Xilinx is introduced, and some of the design challenges this offers for designers and CAD developers are highlighted.
Abstract: This paper introduces a new hybrid ASIC/FPGA chip architecture that is being developed in collaboration between IBM and Xilinx, and highlights some of the design challenges this offers for designers and CAD developers. We review recent data from both the ASIC and FPGA industries, including technology features, and trends in usage and costs. This background data indicates that there are advantages to using standard ASICs and FPGAs for many applications, but technical and financial considerations are increasingly driving the need for a hybrid ASIC/FPGA architecture at specific volume tiers and technology nodes. As we describe the hybrid chip architecture ,we point out evolving tool and methodology issues that will need to be addressed to enable customers to effectively design hybrid ASIC/FPGAs. The discussion highlights specific automation issues in the areas of logic partitioning, logic simulation, verification, timing, layout and test.

328 citations

Proceedings ArticleDOI
08 Dec 2008
TL;DR: This paper experimentally demonstrates correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90 nm test chips and presents an aging-aware timing analysis technique to strategically place such flip-Flop designs at selective locations inside a chip for effective circuit failure prediction.
Abstract: Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias-Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90 nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90 nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.

146 citations

Journal ArticleDOI
TL;DR: An extensive fault simulation infrastructure is developed which allows injection of stuck-at faults and transient errors of arbitrary starting time and duration, as well as cost-effective simulation and classification of their repercussions into various instruction-level error types.
Abstract: We investigate the correlation between low-level faults in the control logic of a modern microprocessor and their instruction-level impact on the execution of typical workload. Such information can prove immensely useful in accurately assessing and prioritizing faults with regards to their criticality, as well as commensurately allocating resources to enhance online testability and error/fault resilience through concurrent error detection/correction methods. To this end, we developed an extensive fault simulation infrastructure which allows injection of stuck-at faults and transient errors of arbitrary starting time and duration, as well as cost-effective simulation and classification of their repercussions into various instruction-level error types. As a test vehicle for our study, we employ a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer benchmarks. Extensive fault injection campaigns in control modules of this microprocessor facilitate valuable observations regarding the distribution of low-level faults into the instruction-level error types that they cause. Experimentation with both Register Transfer (RT-) and Gate-Level faults, as well as with both stuck-at faults and transient errors, confirms the validity and corroborates the utility of these observations.

62 citations

Proceedings ArticleDOI
24 Jun 2008
TL;DR: This paper presents trace-based fault diagnosis, a diagnosis strategy that identifies permanent faults in microarchitectural units by analyzing the faulty corepsilas instruction trace and is a highly robust and flexible way for diagnosing permanent faults.
Abstract: As devices continue to scale, future shipped hardware will likely fail due to in-the-field hardware faults. As traditional redundancy-based hardware reliability solutions that tackle these faults will be too expensive to be broadly deployable, recent research has focused on low-overhead reliability solutions. One approach is to employ low-overhead (ldquoalways-onrdquo) detection techniques that catch high-level symptoms and pay a higher overhead for (rarely invoked) diagnosis. This paper presents trace-based fault diagnosis, a diagnosis strategy that identifies permanent faults in microarchitectural units by analyzing the faulty corepsilas instruction trace. Once a fault is detected, the faulty core is rolled back and re-executes from a previous checkpoint, generating a faulty instruction trace and recording the microarchitecture-level resource usage. A diagnosis process on another fault-free core then generates a fault-free trace which it compares with the faulty trace to identify the faulty unit. Our result shows that this approach successfully diagnoses 98% of the faults studied and is a highly robust and flexible way for diagnosing permanent faults.

52 citations

01 Jan 2000
TL;DR: This thesis examines the problem of combining reconfigurable hardware with a conventional processor into a single-chip device that can serve as the core of a general-purpose computer.
Abstract: As VLSI technology continues to improve, configurable hardware devices such as PLDs are progressively replacing many specialized digital integrated circuits. Field-programmable gate arrays (FPGAs) are one class of such devices, characterized by their ability to be reconfigured as often as desired. Lately, FPGAs have advanced to the stage where they can host large computational circuits, giving rise to the study of reconfigurable computing as a potential alternative to traditional microprocessors. Most previous reconfigurable computers, however, have been ad hoc designs that are not fully compatible with existing general-purpose computing paradigms. This thesis examines the problem of combining reconfigurable hardware with a conventional processor into a single-chip device that can serve as the core of a general-purpose computer. The impact of memory cache stalls, of multitasking context switches, and of virtual memory page faults on the design of the reconfigurable hardware is considered. A possible architecture for the device is defined in detail and its implementation in VLSI studied. With basic development tools and a full-fledged simulator, several benchmarks are tested on the proposed architecture and their performance compared favorably against an existing Sun UltraSPARC. Some additional experiences with the architecture are also related, followed by suggestions for future research.

49 citations