scispace - formally typeset
Open AccessJournal ArticleDOI

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Reads0
Chats0
TLDR
The optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime.
Abstract
This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-state-aging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-time-aging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.

read more

Content maybe subject to copyright    Report

Citations
More filters
Journal ArticleDOI

Methods for fault tolerance in networks-on-chip

TL;DR: The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years.
Proceedings ArticleDOI

Reliable on-chip systems in the nano-era: lessons learnt and future trends

TL;DR: In this article, the authors introduce the most prominent reliability concerns from today's points of view and roughly recapitulate the progress in the community so far and suggest a way for coping with reliability challenges in upcoming technology nodes.
Journal ArticleDOI

At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

TL;DR: This work proposes a distributed functional test mechanism for NoCs which scales to large-scale networks with general topologies and routing algorithms and achieves 100 percent stuck-at fault coverage for the data path and 85 percent for the control paths including routing logic, FIFO's control path, and the arbiter of a 5 × 5 router.
Proceedings ArticleDOI

Workload dependent NBTI and PBTI analysis for a sub-45nm commercial microprocessor

TL;DR: In this article, the authors present an instance-based simulation flow, which creates a standard-cell library for each use of the cell in the design, by aging each transistor individually.
References
More filters
Book

Dynamic Programming and Optimal Control

TL;DR: The leading and most up-to-date textbook on the far-ranging algorithmic methododogy of Dynamic Programming, which can be used for optimal control, Markovian decision problems, planning and sequential decision making under uncertainty, and discrete/combinatorial optimization.
Journal ArticleDOI

Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas

TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Journal ArticleDOI

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

Shekhar Borkar
- 01 Nov 2005 - 
TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
Proceedings ArticleDOI

Temperature-aware microarchitecture

TL;DR: HotSpot is described, an accurate yet fast model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package that shows that power metrics are poor predictors of temperature, and that sensor imprecision has a substantial impact on the performance of DTM.
Journal ArticleDOI

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

TL;DR: The negative bias temperature instability (NBTI) commonly observed in p-channel metaloxide-semiconductor field effect transistors when stressed with negative gate voltages at elevated temperatures is discussed in this article.
Related Papers (5)