Semiconductor wafer bonding
TL;DR: Wafer bonding allows a new degree of freedom in design and fabrication of material combinations that previously would have been excluded because these material combinations cannot be realized by the conventional approach of epitaxial growth.
Abstract: When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical devices. The basics of wafer-bonding technology are described, including microcleanroom approaches, prevention of interface bubbles, bonding of III-V compounds, low-temperature bonding, ultra-high vacuum bonding, thinning methods such as smart-cut procedures, and twist wafer bonding for compliant substrates. Wafer bonding allows a new degree of freedom in design and fabrication of material combinations that previously would have been excluded because these material combinations cannot be realized by the conventional approach of epitaxial growth.
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TL;DR: In this paper, a GaAs-based top tandem solar cell structure was bonded to an InP-based bottom tandem cell with a difference in lattice constant of 3.7%.
Abstract: Triple-junction solar cells from III–V compound semiconductors have thus far delivered the highest solar-electric conversion efficiencies. Increasing the number of junctions generally offers the potential to reach even higher efficiencies, but material quality and the choice of bandgap energies turn out to be even more importance than the number of junctions. Several four-junction solar cell architectures with optimum bandgap combination are found for lattice-mismatched III–V semiconductors as high bandgap materials predominantly possess smaller lattice constant than low bandgap materials. Direct wafer bonding offers a new opportunity to combine such mismatched materials through a permanent, electrically conductive and optically transparent interface. In this work, a GaAs-based top tandem solar cell structure was bonded to an InP-based bottom tandem cell with a difference in lattice constant of 3.7%. The result is a GaInP/GaAs//GaInAsP/GaInAs four-junction solar cell with a new record efficiency of 44.7% at 297-times concentration of the AM1.5d (ASTM G173-03) spectrum. This work demonstrates a successful pathway for reaching highest conversion efficiencies with III–V multi-junction solar cells having four and in the future even more junctions. Copyright © 2014 John Wiley & Sons, Ltd.
562 citations
Cites background from "Semiconductor wafer bonding"
...Two crystal structures are brought closely together forming atomic bonds at the interface [10,11]....
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TL;DR: A review of the state-of-the-art polymer adhesive wafer bonding technologies, materials, and applications can be found in this paper, where the main advantages of this technique include the insensitivity to surface topography, the low bonding temperatures, the compatibility with standard integrated circuit wafer processing, and the ability to join different types of wafers.
Abstract: Wafer bonding with intermediate polymer adhesives is an important fabrication technique for advanced microelectronic and microelectromechanical systems, such as three-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive bears the forces involved to hold the surfaces together. The main advantages of adhesive wafer bonding include the insensitivity to surface topography, the low bonding temperatures, the compatibility with standard integrated circuit wafer processing, and the ability to join different types of wafers. Compared to alternative wafer bonding techniques, adhesive wafer bonding is simple, robust, and low cost. This article reviews the state-of-the-art polymer adhesive wafer bonding technologies, materials, and applications.
494 citations
01 Aug 1998
TL;DR: Wafer-to-wafer bonding processes for microstructure fabrication are categorized and described in this article, which have an impact in packaging and structure design, including direct bonds, anodic bonds and bonds with intermediate layers.
Abstract: Wafer-to-wafer bonding processes for microstructure fabrication are categorized and described. These processes have an impact in packaging and structure design. Processes are categorized into direct bonds, anodic bonds, and bonds with intermediate layers. Representative devices using wafer-to-wafer bonding are presented. Processes and methods for characterization of a range of bonding methods are discussed. Opportunities for continued development are outlined.
478 citations
Cites background or methods from "Semiconductor wafer bonding"
...The imaging methods are nondestructive and can be used as in-process monitors, while the cross-sectional analysis and bondstrength measurements are destructive and require control wafers for characterization....
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...In this section, we will discuss the methods as applied to silicon direct bonding, but many of these same techniques can be applied to other methods of bonding....
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...The emphasis will be placed on silicon direct bonding....
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...It has been shown that when wafers are contacted in air, and subsequently annealed at high temperature, the oxygen in the cavity can react with the silicon surface and create a partial vacuum [34]....
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...In the following sections, we will begin with a description of the silicon direct bonding process, discuss characterization methods for the silicon bond that generalize to all bonding methods, and investigate bonding methods for other types of substrates....
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Patent•
21 Apr 2006
TL;DR: In this article, an intermediate substrate is defined as a handle substrate bonded to a thin layer suitable for epitaxial growth of a compound semiconductor layer, such as a III-nitride semiconductor.
Abstract: An intermediate substrate includes a handle substrate bonded to a thin layer suitable for epitaxial growth of a compound semiconductor layer, such as a III-nitride semiconductor layer. The handle substrate may be a metal or metal alloy substrate, such as a molybdenum or molybdenum alloy substrate, while the thin layer may be a sapphire layer. A method of making the intermediate substrate includes forming a weak interface in the source substrate, bonding the source substrate to the handle substrate, and exfoliating the thin layer from the source substrate such that the thin layer remains bonded to the handle substrate.
456 citations
444 citations
References
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Book•
01 Jan 1985
TL;DR: The forces between atoms and molecules are discussed in detail in this article, including the van der Waals forces between surfaces, and the forces between particles and surfaces, as well as their interactions with other forces.
Abstract: The Forces between Atoms and Molecules. Principles and Concepts. Historical Perspective. Some Thermodynamic Aspects of Intermolecular Forces. Strong Intermolecular Forces: Covalent and Coulomb Interactions. Interactions Involving Polar Molecules. Interactions Involving the Polarization of Molecules. van der Waals Forces. Repulsive Forces, Total Intermolecular Pair Potentials, and Liquid Structure. Special Interactions. Hydrogen-Bonding, Hydrophobic, and Hydrophilic Interactions. The Forces between Particles and Surfaces. Some Unifying Concepts in Intermolecular and Interparticle Forces. Contrasts between Intermolecular, Interparticle, and Intersurface Forces. van der Waals Forces between Surfaces. Electrostatic Forces between Surfaces in Liquids. Solvation, Structural and Hydration Forces. Steric and Fluctuation Forces. Adhesion. Fluid-Like Structures and Self-Assembling Systems. Micelles, Bilayers, and Biological Membranes. Thermodynamic Principles of Self-Assembly. Aggregation of Amphiphilic Molecules into Micelles, Bilayers, Vesicles, and Biological Membranes. The Interactions between Lipid Bilayers and Biological Membranes. References. Index.
18,048 citations
IBM1
TL;DR: In this paper, it was shown that the interfaces between layers were made up of large coherent areas separated by long straight misfit dislocations and the Burgers vectors were inclined at 45° to (001) and were of type 1/2a.
3,179 citations
Book•
31 Mar 1991
TL;DR: In this paper, the authors present a set of techniques for defect detection in SOI materials, including the following: 2.1.1 Silicon-on-Zirconia (SOZ), 2.2.2 E-beam recrystallization, 2.3.3, 3.4.4, and 3.5.5 Other defect assessment techniques.
Abstract: 1 Introduction.- 2 SOI Materials.- 2.1 Introduction.- 2.2 Heteroepitaxial techniques.- 2.2.1 Silicon-on-Sapphire (SOS).- 2.2.2 Other heteroepitaxial SOI materials.- 2.2.2.1 Silicon-on-Zirconia (SOZ).- 2.2.2.2 Silicon-on-Spinel.- 2.2.2.3 Silicon on Calcium Fluoride.- 2.3 Dielectric Isolation (DI).- 2.4 Polysilicon melting and recrystallization.- 2.4.1 Laser recrystallization.- 2.4.2 E-beam recrystallization.- 2.4.3 Zone-melting recrystallization.- 2.5 Homoepitaxial techniques.- 2.5.1 Epitaxial lateral overgrowth.- 2.5.2 Lateral solid-phase epitaxy.- 2.6 FIPOS.- 2.7 Ion beam synthesis of a buried insulator.- 2.7.1 Separation by implanted oxygen (SIMOX).- 2.7.1.1 "Standard"SIMOX.- 2.7.1.2 Low-dose SIMOX.- 2.7.1.3 ITOX.- 2.7.1.4 SMOXMLD.- 2.7.1.5 Related techniques.- 2.7.1.6 Material quality.- 2.7.2 Separation by implanted nitrogen (SIMNI).- 2.7.3 Separation by implanted oxygen and nitrogen (SIMON).- 2.7.4 Separation by implanted Carbon.- 2.8 Wafer Bonding and Etch Back (BESOI).- 2.8.1 Hydrophilic wafer bonding.- 2.8.2 Etch back.- 2.9 Layer transfer techniques.- 2.9.1 Smart-Cut(R).- 2.9.1.1 Hydrogen / rare gas implantation.- 2.9.1.2 Bonding to a stiffener.- 2.9.1.3 Annealing.- 2.9.1.4 Splitting.- 2.9.1.5 Further developments.- 2.9.2 Eltran(R).- 2.9.2.1 Porous silicon formation.- 2.9.2.2 The original Eltran(R) process.- 2.9.2.3 Second-generation Eltran(R) process.- 2.9.3 Transferred layer material quality.- 2.10 Strained silicon on insulator (SSOI).- 2.11 Silicon on diamond.- 2.12 Silicon-on-nothing (SON).- 3 SOI Materials Characterization.- 3.1 Introduction.- 3.2 Film thickness measurement.- 3.2.1 Spectroscopic reflectometry.- 3.2.2 Spectroscopic ellipsometry.- 3.2.3 Electrical thickness measurement.- 3.3 Crystal quality.- 3.3.1 Crystal orientation.- 3.3.2 Degree of crystallinity.- 3.3.3 Defects in the silicon film.- 3.3.3.1 Most common defects.- 3.3.3.2 Chemical decoration of defects.- 3.3.3.3 Detection of defects by light scattering.- 3.3.3.4 Other defect assessment techniques.- 3.3.3.5 Stress in the silicon film.- 3.3.4 Defects in the buried oxide.- 3.3.5 Bond quality and bonding energy.- 3.4 Carrier lifetime.- 3.4.1 Surface Photovoltage.- 3.4.2 Photoluminescence.- 3.4.3 Measurements on MOS transistors.- 3.4.3.1 Accumulation-mode transistor.- 3.4.3.2 Inversion-mode transistor.- 3.4.3.3 Bipolar effect.- 3.5 Silicon/Insulator interfaces.- 3.5.1 Capacitance measurements.- 3.5.2 Charge pumping.- 3.5.3 ?-MOSFET.- 4 SOI CMOS Technology.- 4.1 SOI CMOS processing.- 4.1.1 Fabrication yield and fabrication cost.- 4.2 Field isolation.- 4.2.1 LOCOS.- 4.2.2 Mesa isolation.- 4.2.3 Shallow trench isolation.- 4.2.4 Narrow-channel effects.- 4.3 Channel doping profile.- 4.4 Source and drain engineering.- 4.4.1 Silicide source and drain.- 4.4.2 Elevated source and drain.- 4.4.3 Tungsten clad.- 4.4.4 Schottky source and drain.- 4.5 Gate stack.- 4.5.1 Gate material.- 4.5.2 Gate dielectric.- 4.5.3 Gate etch.- 4.6 SOI MOSFET layout.- 4.6.1 Body contact.- 4.7 SOI-bulk CMOS design comparison.- 4.8 ESD protection.- 5 The SOI MOSFET.- 5.1 Capacitances.- 5.1.1 Source and drain capacitance.- 5.1.2 Gate capacitance.- 5.2 Fully and partially depleted devices.- 5.3 Threshold voltage.- 5.3.1 Body effect.- 5.3.2 Short-channel effects.- 5.4 Current-voltage characteristics.- 5.4.1 Lim & Fossum model.- 5.4.2 C?-continuous model.- 5.5 Transconductance.- 5.5.1 gm/ID ratio.- 5.5.2 Mobility.- 5.6 Basic parameter extraction.- 5.6.1 Threshold voltage and mobility.- 5.6.2 Source and drain resistance.- 5.7 Subthreshold slope.- 5.8 Ultra-thin SOI MOSFETs.- 5.8.1 Threshold voltage.- 5.8.2 Mobility.- 5.9 Impact ionization and high-field effects.- 5.9.1 Kink effect.- 5.9.2 Hot-carrier degradation.- 5.10 Floating-body and parasitic BJT effects.- 5.10.1 Anomalous subthreshold slope.- 5.10.2 Reduced drain breakdown voltage.- 5.10.3 Other floating-body effects.- 5.11 Self heating.- 5.12 Accumulation-mode MOSFET.- 5.12.1 I-V characteristics.- 5.12.2 Subthreshold slope.- 5.13 Unified body-effect representation.- 5.14 RF MOSFETs.- 5.15 CAD models for SOI MOSFETs.- 6 Other SOI Devices.- 6.1 Multiple-gate SOI MOSFETs.- 6.1.1 Multiple-gate SOI MOSFET structures.- 6.1.1.1 Double-gate SOI MOSFETs.- 6.1.1.2 Triple-gate SOI MOSFETs.- 6.1.1.3 Surrounding-gate SOI MOSFETs.- 6.1.1.4 Triple-plus gate SOI MOSFETs..- 6.1.2 Device characteristics.- 6.1.2.1 Current drive.- 6.1.2.2 Short-channel effects.- 6.1.2.3 Threshold voltage.- 6.1.2.4 Volume inversion.- 6.1.2.5 Mobility.- 6.2 MTCMOS/DTMOS.- 6.3 High-voltage devices.- 6.3.1 VDMOS and LDMOS.- 6.3.2 Other high-voltage devices.- 6.4 Junction Field-Effect Transistor.- 6.5 Lubistor.- 6.6 Bipolar junction transistors.- 6.7 Photodiodes.- 6.8 G4 FET.- 6.9 Quantum-effect devices.- 7 The SOI MOSFET in a Harsh Environment.- 7.1 Ionizing radiations.- 7.1.1 Single-event phenomena.- 7.1.2 Total dose effects.- 7.1.3 Dose-rate effects.- 7.2 High-temperature operation.- 7.2.1 Leakage current.- 7.2.2 Threshold voltage.- 7.2.3 Output conductance.- 7.2.4 Subthreshold slope.- 8 SOI Circuits.- 8.1 Introduction.- 8.2 Mainstream CMOS applications.- 8.2.1 Digital circuits.- 8.2.2 Low-voltage, low-power digital circuits.- 8.2.3 Memory circuits.- 8.2.3.1 Non volatile memory devices.- 8.2.3.2 Capacitorless DRAM.- 8.2.4 Analog circuits.- 8.2.5 Mixed-mode circuits.- 8.3 Niche applications.- 8.3.1 High-temperature circuits.- 8.3.2 Radiation-hardened circuits.- 8.3.3 Smart-power circuits.- 8.4 Three-dimensional integration.
1,627 citations
"Semiconductor wafer bonding" refers background or methods in this paper
...From then on, silicon wafer bonding and the associated thinning techniques were further investigated and improved for the fabrication of SOI wafers, as a supposedly less expensive and better quality alternative to the SIMOX (Separation by IMplantation of OXygen) approach, which involves high-dose and high-energy oxygen implantation (16, 17)....
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...The subject of SOI devices has been treated extensively elsewhere (16, 17) and is not specifically discussed in this review....
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TL;DR: In this article, a silicon on insulator material technology based on wafer bonding is described, in which a heat treatment induces an in-depth microslicing of one of the two bonded wafers previously implanted with hydrogen.
Abstract: A silicon on insulator material technology based on wafer bonding is described, in which a heat treatment induces an in-depth microslicing of one of the two bonded wafers previously implanted with hydrogen. The basic phenomena, and the first physical and electrical characterisations are discussed briefly.
1,106 citations
TL;DR: In this paper, conditions for the selective lift-off of large area epitaxial AlxGa1−xAs films from the substrate wafers on which they were grown were discovered.
Abstract: We have discovered conditions for the selective lift‐off of large area epitaxial AlxGa1−xAs films from the substrate wafers on which they were grown. A 500‐A‐thick AlAs release layer is selectivity etched away, leaving behind a high‐quality epilayer and a reusable GaAs substrate. We have measured a selectivity of ≳107 between the release layer and Al0.4Ga0.6As. This process relies upon the creation of a favorable geometry for the outdiffusion of dissolved H2 gas from the etching zone.
895 citations