Semicustom power gating design
21 Jul 2011-pp 471-474
TL;DR: The main aim is to implement power gating in semicustom design, which is applied to 8 bit RISC architecture by using Design Architect from MENTOR GRAPHICS with the modified ADK library.
Abstract: Sub threshold leakage current has increased dramatically with technology scaling and it consumes a significant portion of the total power. In order to reduce the leakage current, one of the efficient method is power gating. The main challenge in power gating is, to design switching fabric and power controller. In this paper the main aim is to implement power gating in semicustom design. For this we implement a power controller for the design, insert sleep transistors and size the sleep transistors. According to the input, the power controller generates the signal to decide which block is to turn ON and which one is to turn OFF. The switching transistors such as header or footer are inserted in to the design, which act as switches. Sizing of the sleep transistors is essential in order to reduce the long wake up delays. The proposed methodology is applied to 8 bit RISC architecture by using Design Architect from MENTOR GRAPHICS with the modified ADK library.
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Proceedings Article•
11 Oct 2012TL;DR: This paper presents a method of implementing power gating that does not require special digital cells, it is easy to size and includes soft start and monitor functions.
Abstract: Embedded systems need to save as much energy as possible in order to prolong the battery life. Many applications only require the use of the system for a brief period of time followed by a long stand-by phase. Static currents in digital systems can drag large amounts of charge, particularly at high temperatures. Power gating has been used to reduce the impact of these currents but it is difficult to include it in the digital design flow. This paper presents a method of implementing power gating that does not require special digital cells, it is easy to size and includes soft start and monitor functions.
1 citations
References
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20 Apr 2009
TL;DR: A layout-oriented synthesis flow which integrates the two techniques and that relies on leading-edge, commercial EDA tools and that achieves runtime leakage reduction by inserting dedicated sleep transistors for each cluster.
Abstract: Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way that the clock-gating information can be used to drive the control signal of the power-gating circuitry, thus providing additional leakage minimization conditions w.r.t. those manually inserted by the designer. This conceptual integration, however, poses several challenges when moved to industrial design flows. Although both clock and power-gating are supported by most commercial synthesis tools, their combined implementation requires some flexibility in the back-end tools that is not currently available. This paper presents a layout-oriented synthesis flow which integrates the two techniques and that relies on leading-edge, commercial EDA tools. Starting from a gated-clock netlist, we partition the circuit in a number of clusters that are implicitly determined by the groups of cells that are clock-gated by the same register. Using a row-based granularity, we achieve runtime leakage reduction by inserting dedicated sleep transistors for each cluster. The entire flow has been benchmarked on a industrial design mapped onto a commercial, 65nm CMOS technology library.
34 citations
TL;DR: A semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed and a new power network architecture is proposed for cell-based power gating circuits.
Abstract: The application of power gating to cell-based semi- custom design typically calls for customized cell libraries, which incurs substantial engineering efforts. In this brief, a semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed. In particular, a new power network architecture is proposed for cell-based power gating circuits. The impact of body bias on current switch design and the layout method of current switch for flexible placement are investigated. The circuit elements that supplement cell-based power gating design are then discussed, including output interface circuits and state retention flip-flops. The proposed methodology is applied to ISCAS benchmark circuits and to a commercial Viterbi decoder with 0.18-mum CMOS technology.
31 citations
28 Apr 2009
TL;DR: This paper presents an interface planning methodology, and takes a DVFS and power gating design with over 50 power domains and 80 power modes to demonstrate the verification challenges and the solutions and proposes a “seamless” interface control circuit for PSO and DVFS designs.
Abstract: Reducing the power supply voltage is an effective technique to reduce dynamic power. Power shut-off (PSO) is also a well-known approach to reduce leakage power. In practice, one may employ multi-supply voltage or dynamic voltage and frequency scaling (DVFS) techniques accompanied with power gating and multi-depth sleep modes to reduce both of dynamic and leakage power consumption. As the voltage domains (power domains) and sleep modes (power modes) are increased dramatically, it is difficult to plan interface logics such as level shifters and isolation cells completely by manual for each power domain. In this paper, we present an interface planning methodology, and take a DVFS and power gating design with over 50 power domains and 80 power modes to demonstrate the verification challenges and our solutions. Besides, we propose a “seamless” interface control circuit for PSO and DVFS designs. By using the circuit, the designs in the power on domain don't feel any data change when the opposite power domain is powered off.
14 citations
IBM1
TL;DR: This work proposes a methodology in which it proves sequential equivalence between the power gated design and a simplified version of itself, then uses the simplified version in a binary simulation.
Abstract: Power gating is a technique for low power design in which whole sections of the chip are powered off when they are not needed, and powered back on when they are. Functional correctness of power gating is usually checked at the system level, where the most widely used technique is simulation using pseudo-random stimuli. This normally entails running extremely expensive ternary simulations, in order to model the memory loss that occurs as a result of a memory element being powered off. We propose instead a methodology in which we prove sequential equivalence between the power gated design and a simplified version of itself, then use the simplified version in a binary simulation. We use a compositional approach that looks for partial equivalence of each unit under a suitable set of assumptions, guaranteed by the neighboring units. The partial equivalences are then composed into total equivalence on the whole chip. Our method is applicable to any power gated design, no matter the side effects (e.g., in timing of events across the interfaces) caused by the particular implementation of power gating.
10 citations
26 Mar 2007
TL;DR: A new power network architecture is proposed that allows unmodified conventional logic cells to be used in cell-based semi-custom design of ZPG circuits and circuit elements that supplement the cell- based ZPG design are discussed.
Abstract: Zigzag power gating (ZPG) has been proposed to overcome the drawback of power gating in its long wakeup delay. However, the use of both NMOS and PMOS current switches in zigzag fashion makes power networks very complicated. This has limited the application of ZPG circuits only to custom design. This paper proposes cell-based semi-custom design of ZPG circuits. A new power network architecture is proposed that allows unmodified conventional logic cells to be used. The circuit elements that supplement the cell-based ZPG design are then discussed. To optimize the physical design of ZPG circuits, two methods are proposed. The area is optimized by modulating the number of different types of circuit rows. The wirelength is optimized by selecting the sleep vector that leads to shorter wirelength between flip-flops and their fanin and fanout gates
7 citations
"Semicustom power gating design" refers background in this paper
...Footer connected rows are between Vdd & VSSY' In HCR body is connected to V ss and in FCR it is connected to V SSY' The use of both header and footer in zigzag fashion has a drawback of complicated power networks....
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...The transistor is sized according to the time by which it wakes up and down[3]....
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...978-1-61284-653-8/11/$26.00 ©2011 IEEE Header Connected Row(HCR) is between V ddy & V sso the gates that are logic low are placed in HCR's....
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...The area overhead increases due to n well isolation in HCR[3]....
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