SHAKTI-MS: a RISC-V processor for memory safety in C
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Cites background from "SHAKTI-MS: a RISC-V processor for m..."
...However, while there is no change in processor clock frequency in [21], MSMPX reduced the maximum clock frequency of the processor by around 6....
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...hardware based solutions [21], where the hardware overhead...
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References
2,540 citations
"SHAKTI-MS: a RISC-V processor for m..." refers background or methods in this paper
...Location based [15, 17, 31, 41] approaches use an extra data structure such as a tree or it uses a hashtable/trie-based implementation of shadow memory space to keep track of the allocated and deallocated memory regions....
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...There have been many solutions proposed to mitigate temporal attacks [2, 3, 9, 10, 15, 29, 31, 32, 35, 41, 42]....
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1,536 citations
"SHAKTI-MS: a RISC-V processor for m..." refers background in this paper
...Many of these attacks have mitigations in place, such as making the stack non-executable [40] or adding stack canaries [11] to detect tampering of return address....
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1,367 citations
"SHAKTI-MS: a RISC-V processor for m..." refers background in this paper
...Moreover, spatial attacks like buffer overflow have evolved over time and given rise to more sophisticated techniques like return-to-libc [38] or Return Oriented Programming (ROP) [37]....
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1,236 citations
"SHAKTI-MS: a RISC-V processor for m..." refers background in this paper
...While these devices are becoming more pervasive, large scale attacks involving compromised embedded devices such as the Mirai botnet [21] are becoming commonplace....
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