Short circuit power estimation of static CMOS circuits
30 Jan 2001-pp 545-550
TL;DR: It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.
Abstract: This paper presents a simple method to estimate short-circuit power dissipation for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.
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25 Sep 2006
TL;DR: A brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power V LSI circuits is presented.
Abstract: The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods
420 citations
24 May 2009
TL;DR: The proposed model is used for calculating inverter delays for different input transition times, load capacitances and supply voltages, and is in good agreement with those of transistor level simulation results from SPICE.
Abstract: This paper presents a new analytical propagation delay model for nanoscale CMOS inverters. By using a non-saturation current model, the analytical input-output transfer responses and propagation delay model are derived. The model is used for calculating inverter delays for different input transition times, load capacitances and supply voltages. Delays predicted by the proposed model are in good agreement with those of transistor level simulation results from SPICE, with accuracy of 3% or better.
32 citations
Cites background or methods from "Short circuit power estimation of s..."
...For extracting the propagation delay, development of a delay model for a CMOS inverter is considered as the first step [14], and a number of inverter delay models have been developed [6-15]....
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...A circuit’s speed/frequency and dynamic power dissipation are both affected significantly by propagation delay, and hence timing analysis has been investigated for several decades [1-7]....
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01 Jan 2006
TL;DR: In this article, the authors present a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power very large scale integration (VLSI) circuits.
Abstract: The growing packing density and power con- sumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnec- tions. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an over- view of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.
14 citations
Dissertation•
17 Oct 2017
TL;DR: In this article, a methode pratique and efficace d'estimation de the consommation, including a base de donnees issue de simulations, and a theoryique des taux d'activite de chaque element de la chaine.
Abstract: La forte augmentation du nombre de terminaux connectes ces dernieres annees et l'utilisation croissante des technologies de communication impacte de maniere non negligeable la facture energetique. Pour enrayer cette augmentation de la consommation energetique, il devient primordial de pouvoir comparer en termes de consommation les algorithmes de communications numeriques, afin de developper l'architecture de transmission la moins energivore. Dans cette these, la couche physique des standards Wi-Fi IEEE 802.11ac est analysee sous un angle energetique. La puissance dissipee dans les circuits pour faire fonctionner les algorithmes de traitement de signal est prise en compte en plus de la puissance d'emission d'antenne classique. La methodologie mise en œuvre inclut a la fois des simulations et des developpements sur plateforme materielle (FPGA), permettant d'obtenir des evaluations de la consommation plus realistes. Nous avons dans un premier temps analyse de facon isolee les elements composant les chaines de communications numeriques. Puis nous avons integre les periodes d'activite et d'inactivite de chaque element dans le calcul de la consommation energetique globale des chaines. Nous proposons une methode pratique et efficace d'estimation de la consommation, incluant une base de donnees issue de simulations, et une analyse theorique des taux d'activite de chaque element de la chaine. Ces resultats permettent d'analyser la repartition de la consommation en puissance des elements composant les emetteurs et les recepteurs, et de comparer diverses architectures et jeux de parametres. En particulier, nous avons evalue l'impact de deux architectures de Transformees de Fourier Rapides sur la consommation globale du systeme.
4 citations
Cites background from "Short circuit power estimation of s..."
...Il est possible de trouver dans l’état de l’art différentes propositions de modélisation de ce courant [12][13][14]....
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References
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TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION
3,156 citations
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Abstract: An alpha -power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square-law MOS model in the saturation region. Since the model is simple, it can be used to handle MOSFET circuits analytically and can predict the circuit behavior in the submicrometer region. Using the model, closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived. The delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is found that the CMOS inverter delay becomes less sensitive to the input waveform slope and that short-circuit dissipation increases as the carrier velocity saturation effect in short-channel MOSFETs gets more severe. >
1,596 citations