Si Nanowire CMOS Transistors and Circuits by Top-Down Technology Approach
05 May 2008-Vol. 13, Iss: 1, pp 201-211
About: The article was published on 2008-05-05. It has received 2 citations till now. The article focuses on the topics: CMOS & Nanowire.
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03 Aug 2010
TL;DR: The newly introduced vertically-stacked silicon nanowire gate-all-around field-effect-transistor technology and its advantages for higher density layout design and reduction in silicon active area occupancy are envisaged of great significance for regular cell mapping, in disruptive future applications based on nanowires transistor arrays.
Abstract: This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around field-effect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangement of nanowire transistors with near-ideal characteristics, and opens the possibility for design optimization by adjusting the number of nanowire stacks without affecting the footprint area of the device. Several libraries for combinational logic synthesis have been designed and implemented for the synthesis of carry-lookahead adders, using the vertically-stacked nanowire technology. The reduction in silicon active area occupancy of vertically-stacked gates are envisaged of great significance for regular cell mapping, in disruptive future applications based on nanowire transistor arrays.
10 citations
Cites background from "Si Nanowire CMOS Transistors and Ci..."
...However, only a few works have assessed the impact of nanowire technology in complex circuits [7], [8]....
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01 Aug 2016
TL;DR: In this article, a new model for predicting the static characteristics of nanowire CMOS (NW-CMOS) inverter is proposed. This model depends on experimental (or simulated) output characteristics of load and driver transistors separately as an input data.
Abstract: This This paper is to suggest a new model for predicting the static characteristics of nanowire-CMOS (NW-CMOS) inverter. This model depends on experimental (or simulated) output characteristics of load and driver transistors separately as an input data. This model used in this research to investigate the effect of length (L), oxide thickness (Tox) and numbers of nanowires in P and N-channel SiNWT on the NW-CMOS inverter output and current characteristics. This study used MuGFET simulation tool to produce the output characteristics of SiNWT which used as input to a designed MATLAB software to calculate the characteristics of NW-CMOS. The output (Vout-Vin) and current (Iout-Vin) characteristics that calculated shows excellent behaviors for digital applications.