Abstract: The size of a metal-oxide-semiconductor field-effect-transistor (MOSFET) in very-large-scale integrated circuits (VLSI) have been scaled down for higher integration and higher performance However, potential coupling between source and drain becomes prominent as a gate length is shrunk below to sub-50 nm and this provokes large short-channel-effects (SCEs) As a result, gate controllability to surface potential is weakened, and accordingly, subthreshold leak current becomes remarkable In order to obtain high SCE immunity using conventional bulk planar-type MOSFETs, high channel doping concentration is required, but high doping level causes mobility degradation and worsens characteristic fluctuation of MOSFETs Thus, continuous scaling of the conventional bulk planer-type MOSFETs is now facing difficult situation and is challenged by physical and technological limitation Silicon nanowire is one of the most promising structure for future ultra-scaled device due to extremely small size and has two attractive devices: gate-all-around (GAA) nanowire MOSFET (NW FET) and SET/SHT NW FET and SET/SHT are promising devices for ultra scaled nano regime device due to superior SCE immunity and high functionality, respectively By recent progress in silicon nano-structure fabrication technique, high performance NW FETs having uniform channel size is fabricated, and large Coulomb blockade oscillation in SET/SHT is observed even at room-temperature On the other hands, strain technology is extensively investigated for mobility enhancement in MOSFET However, most of the studies have paid attention only to three-dimensional (3D) or two-dimensional (2D) channel MOSFETs, not to ultra-nano scaled one-dimensional (1D) or zero-dimensional (0D) devices, such as NW FET and SET/SHT Although driving current is gradually not affected by mobility term as device scaled to sub-20 nm because ballistic transport becomes dominant, effective mass which determines incidence velocity is still influential on drain current and the effective mass is controllable by using strain technology Also, strain in SET/SHT is expected to discover new physics of SET/SHT and improve understanding of operation principals Therefore, demonstration of strain technology and confirmation of the effects on the NW FET and SET/SHT are strongly desired The objective of this work is to investigate the strain technology in the future nano-scaled NW FET and SET/SHT We confirm the effectiveness of the strain even at ultra narrow NW FET and nanowire size dependency is studied systematically Also, the strain effect on the novel device SET/SHT which is operated by tunneling mechanism is discussed to discover physics of SET/SHT After NW FETs and SETs/SHTs are fabricated by using ultra-narrow channel method, two directions of strain are applied by mechanically In NW FETs, we observe simple strain effects, namely Vth shift and mobility modulation at low Vover and high Vover, respectively NW pFETs provide greater ΔId/Id than NW nFETs, and nanowire width dependency of the effects is observed for the first time only in NW pFETs because the effective mass m* modulation is decreased as nanowire width becomes narrower In SETs/SHTs case, in addition to Vth shift and mobility enhancement, Coulomb blockade oscillation characteristics are changed by the strain While current modulation is very complicated in SETs, strain effects on SHTs are easily analyzed by means of m* modulation More current improvement and characteristics modification can be expected, if relatively larger strain (~ GPa) is applied Acknowledgements The research work described in this dissertation carried out at Institute of Industrial Science, the University of Tokyo, while the author was a graduate student in Department of Electronics Engineering, School of Engineering, the University of Tokyo, from April 2007 to March 2009 This work has been supported by many people and the author would like to take this opportunity to express his gratitude for their help and contribution First of all, the author would like to extend his deepest appreciation to the dissertation supervisor, Prof T Hiramoto, Institute of Industrial Science, the University of Tokyo, for providing appropriate guidance and opportunity to pursue my research This work could not have been accomplished without his continuous encouragement The author would like to thank Prof H Fujita, Prof Y Arakawa, and Prof H Toshiyoshi for kindly providing experimental apparatus for the device fabrication The author is also grateful to Profs K Asada, T Sakurai, T Shibata, S Takagi, and M Takamiya for valuable comments on this work The author would like to thank T Saraya, H Kawai, and W Nagashiro for their technical supports to maintain the experimental instruments and equipments The author would express special thanks to Dr K Miyaji for his unsparing advices for single-electron transistors and kind instructions on the fabrication process The author is really indebted to him for all his help The author is also grateful to the members of Hiramoto Laboratory: P Arifin, J Chen, K Shimizu, K Mao, JS Park, K Takahashi, Y Takahashi, T Mama, R Hashimoto, L Zhu, M Suzuki, R Suzuki, CH Lee, I Yamato, T Kanno for stimulating daily discussions Finally, the author would like to express his gratitude to K Kojima for their assistance in the office work