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Journal ArticleDOI

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Abstract: Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.
Citations
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Journal ArticleDOI
TL;DR: In this article, the authors summarized some of the essential aspects of silicon-nanowire growth and of their electrical properties, including the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs-Thomson effect for the silicon wire growth velocity.
Abstract: This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor–liquid–solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs–Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.

721 citations

Journal ArticleDOI
TL;DR: In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.
Abstract: This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.

297 citations


Cites background from "Si, SiGe Nanowire Devices by Top–Do..."

  • ...(∼70 mV/V) is achieved as a result of excellent gate control by GAA structure [4], [11], and [12]....

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Journal ArticleDOI
19 Feb 2013-ACS Nano
TL;DR: A bit- cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work.
Abstract: The three-dimensional (3D) cross-point array architecture is attractive for future ultra-high-density nonvolatile memory application. A bit-cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work. A double-layer HfOx-based vertical resistive switching random access memory (RRAM) is fabricated and characterized. The HfOx thin film is deposited at the sidewall of the predefined trench by atomic layer deposition, forming a vertical memory structure. Electrode/oxide interface engineering with a TiON interfacial layer results in nonlinear I–V suitable for the selectorless array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current ( 108 cycles), read disturbance immunity (>109 cycles), and data retention time (>105 s @ 125 °C).

294 citations

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, a double-layer stacked HfOx vertical RRAM is demonstrated for 3D crosspoint architecture using a cost-effective fabrication process, and a unique write/read scheme is proposed for 3d cross-point architecture.
Abstract: Double-layer stacked HfOx vertical RRAM is demonstrated for 3D cross-point architecture using a cost-effective fabrication process. Electrode/oxide interface engineering using TiON layer results in non-linear I-V suitable for the selector-less array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current ( 108 cycles), half-selected read disturbance immunity (>109 cycles), retention (>105s @125oC). Moreover, a unique write/read scheme is proposed for 3D cross-point architecture. Analysis shows that for such 3D selector-less array, a large R on (∼100kΩ) from the non-linear I-V helps reduce the sneak path current, and a low interconnect resistance using metal planes as word lines reduces the undesirable voltage drop on the interconnect. As a conservative estimate, simulation shows that Mb-scale array without cell selector is achievable.

175 citations

Journal ArticleDOI
TL;DR: This review provides methods for the synthesis and modification of silicon nanosheets and other silicon nanomaterials with examples of their potential applications and a soft synthetic method for silicon nanOSheets with chemical surface modification in a solution process.
Abstract: Silicon nanomaterials and nanostructures exhibit different properties from those of bulk silicon materials based on quantum confinement effects. They are expected to lead to the development of new applications of silicon, in addition to wide use in semiconductor devices. Aside from industrial interest, intriguing issues of academic interest still remain with respect to the origins of their characteristic properties. Zero- and one-dimensional crystalline silicon nanomaterials have been synthesized, to date, by using many methods and there has been rapid progress in size control and modification procedures. However, there have been only a few examples of silicon nanomaterials with atomic-order thickness akin to carbon nanomaterials, such as two-dimensional silicon nanosheets. Moreover, mass production of silicon nanomaterials with relatively low cost is not easily achievable, due to the typically severe conditions required for fabrication, such as high temperature and ultralow pressure. Recently, we have developed a soft synthetic method for silicon nanosheets with chemical surface modification in a solution process. This review provides methods for the synthesis and modification of silicon nanosheets and other silicon nanomaterials with examples of their potential applications.

160 citations

References
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Journal ArticleDOI
TL;DR: In this article, gate-all-around n-MOSFETs with Si-nanowire as the channel body are fabricated and characterized for their low-temperature behavior.
Abstract: Gate-all-around n-MOSFETs with Si-nanowire (~7 nm) as the channel body are fabricated and characterized for their low-temperature behavior (~5 K to 295 K) IDS-VGS characteristics at low VDS (~50 mV) exhibit a decrease in current with decreasing temperature in strong inversion up to about ~200 K However, at high VDS, drain current reverts to typical temperature behavior, ie, IDS increases with the reducing temperature due to the increase in phonon-limited mobility (muph)- It is inferred that, at low VDS the enhancement in muph at a reduced temperature could be possibly masked by the intersubband scattering on account of subband splitting due to quantum-confinement effects as indicated by subband calculations for nanowire structures

40 citations


"Si, SiGe Nanowire Devices by Top–Do..." refers background in this paper

  • ...Electrical characterization of NW devices at cryogenic temperatures shows the evidence of discrete energy bands as a result of quantum confinement [45]–[48]....

    [...]

Journal ArticleDOI
TL;DR: In this paper, local stress-limited oxidation was used to fabricate silicon quantum wire transistors with a channel diameter of 5 nm, and a novel wraparound gate was employed to improve the gate control of the potential in the channel.
Abstract: Local stress-limited oxidation was used to fabricate silicon quantum wire transistors with a channel diameter of 5 nm. The oxidation of source and drain regions was prevented with a silicon nitride diffusion barrier. A novel wraparound gate was used to improve the gate control of the potential in the channel. The electrical properties of these devices were investigated at room temperature. Ideal subthreshold behavior, with the subthreshold swing equal to 60.3 mV/dec, was observed.

36 citations


Additional excerpts

  • ...[24] made use of this stress-limited oxida-...

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Journal ArticleDOI
TL;DR: In this article, the integration potential of gate-all-around (GAA) Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is demonstrated.
Abstract: We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON–OFF transitions with high voltage-gains (e.g., Δ V OUT /Δ V IN up to ∼45) and symmetric pull-up and pull-down characteristics. The matching of the drive currents of n- and p-MOSFETs is achieved using different number of nanowire channels for N- and P-MOS transistors. The inverter maintains its good transfer characteristics and noise margins for wide range of V DD tested down to 0.2 V. The detailed experimental characterization is discussed along with the electrical characteristics of the individual transistors comprising the inverter. The performances of the inverters are discussed vis-a-vis those reported in the literature using advanced non-classical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is thus demonstrated.

33 citations


"Si, SiGe Nanowire Devices by Top–Do..." refers methods in this paper

  • ...The symmetry in pull-up/pull-down characteristics has been achieved in two different ways, namely, 1) by using a longer n-channel device compared with the p-channel device [51] and 2) by using a larger number of NWs in p-channel transistors [52]–[54]....

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  • ...We have demonstrated CMOS inverters with NW GAA channels using the top–down approach [51]–[54]....

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Proceedings ArticleDOI
05 Dec 2005
TL;DR: In this paper, the authors improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure and achieved a high performance 30 nm/33 nm gate nMOSFET with a drive current of 937/1000 muA/mum.
Abstract: Aggressively scaled 30 nm gate CMOSFETs for 45 nm node is reported We successfully improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure Both hole mobility and source/drain extension (SDE) resistance in pMOSFET are improved by combination of optimized Sigma shaped SiGe-SD and slit-embedded B-doped SiGe-SDE Electron and hole mobility enhancement can be balanced by aggressively scaled poly-Si pMOS gate height and SiN capped shallow trench isolation (STI) with SiN liner A high performance 30 nm/33 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 937/1000 muA/mum and 490/545 muA/mum at Vd=10 V / Ioff=100 nA/mum, respectively

33 citations

Journal ArticleDOI
TL;DR: In this article, a novel channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated.
Abstract: A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current IDSAT improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.

33 citations


"Si, SiGe Nanowire Devices by Top–Do..." refers background in this paper

  • ...stressors in the structure to improve mobility [2], [3]....

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