Journal ArticleDOI
Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
Navab Singh,K.D. Buddharaju,Sanjeev Kumar Manhas,Ajay Agarwal,S.C. Rustagi,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +7 more
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TLDR
The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.Abstract:
Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.read more
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Journal ArticleDOI
Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties
TL;DR: In this article, the authors summarized some of the essential aspects of silicon-nanowire growth and of their electrical properties, including the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs-Thomson effect for the silicon wire growth velocity.
Journal ArticleDOI
Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature
TL;DR: In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.
Journal ArticleDOI
HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture.
TL;DR: A bit- cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work.
Proceedings ArticleDOI
HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector
TL;DR: In this paper, a double-layer stacked HfOx vertical RRAM is demonstrated for 3D crosspoint architecture using a cost-effective fabrication process, and a unique write/read scheme is proposed for 3d cross-point architecture.
Journal ArticleDOI
Synthesis and modification of silicon nanosheets and other silicon nanomaterials.
TL;DR: This review provides methods for the synthesis and modification of silicon nanosheets and other silicon nanomaterials with examples of their potential applications and a soft synthetic method for silicon nanOSheets with chemical surface modification in a solution process.
References
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Proceedings ArticleDOI
A 6-level-metal CMOS process for 0.25-0.18 micron foundry manufacturing
TL;DR: In this article, a 6-level-metal 0.25/spl mu/m CMOS technology, with 6 layers of fully planarized interconnect, has been developed for versatile, flexible, and fast turn-around foundry manufacturing.
Proceedings ArticleDOI
Silicon Nanowire Schottky Barrier NMOS Transistors
E. J. Tan,Kin Leong Pey,Navab Singh,Guo-Qiang Lo,Dongzhi Chi,Keat-Mun Hoe,P.S. Lee and,G. D. Cui +7 more